Abstract: A phase interpolator includes phase interpolator circuitries. The phase interpolator circuitries generate an output clock signal from an output node according to phase control bits and clock signals. Phases of the clock signals are different from each other. Each phase circuitry includes phase buffer circuits. Each phase buffer circuit is turned on according a first bit and a second bit of the phase control bits, in order to generate a signal component in the output clock signal according to a corresponding clock signal of the clock signals. Each phase buffer circuit includes a first resistor and a second resistor, and transmits one of a first voltage and a second voltage to the output node according to the corresponding clock signal, in which the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.

Abstract: Disclosed is a data flow classification device including a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit. The configuring circuit receives and stores the identification and traffic information of multiple flows, and accordingly calculates the traffic of the multiple flows, wherein the multiple flows include the input flow. The configuring circuit further determines an elephant flow threshold according to a queue length of the buffer circuit and a target length, determines the classifications of the multiple flows according to the comparison between the traffic of the multiple flows and the elephant flow threshold, and stores these classifications in the lookup table.

Abstract: The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

Abstract: The application discloses a transceiver, including a calibration signal generation unit, a transmission unit, a receiving unit and a control unit. The calibration signal generation unit generates test signal to the transmission unit in a phase calibration mode. The receiving unit generates a digital receiving signal. The control unit calculates a phase difference between the digital receiving signal and a given reference phase and selectively adjust the transmission unit or the receiving unit accordingly. The application discloses a transceiver calibration method as well.

Abstract: The present invention provides a control module and a control method thereof for an SDRAM. The control module includes at least one register and a controller. The controller is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operating mode; setting value of the at least one register under the DPIN operating mode; and control the SDRAM according to the value of the at least one register.

Abstract: A method includes: generating a first signal according to a digital signal; filtering the first signal according to first filter coefficients of first filter to generate a second signal; adding a first reference signal with the second signal to generate a third signal; performing digital-to-analog conversion according to the first and third signals to generate and output an echo signal; performing analog-to-digital conversion according to the echo signal to generate a fourth signal; generating a fifth signal according to the digital signal and the fourth signal; and updating the first filter coefficients according to the fifth signal.

Abstract: A switch control circuit includes a power switch, a first protection unit, and a second protection unit. The power switch has a first terminal coupled to a first voltage terminal for receiving a first voltage, a second terminal coupled to a second voltage terminal for receiving a second voltage, and a control terminal receives a control voltage. In a first mode, the control voltage is greater than the first voltage. In a second mode, when a voltage of the second voltage terminal is smaller than a first reference voltage, the first protection unit pulls down the control voltage to reduce a current flowing through the power switch. When the voltage of the second voltage terminal is smaller than the second reference voltage, the second protection unit pulls down the control voltage to a ground voltage.

Abstract: An optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuitry. The boost converter circuit is configured to convert a supply voltage according to a pulse width modulation signal, in order to generate an output voltage. The optical receiver circuit is configured to set a gain according to the output voltage, in order to convert an optical signal to a data signal according to the gain. The pulse width modulation controller circuitry is configured to perform a digital to analog conversion according to a control code to gradually adjust a current associated with the output voltage, and to compare the output voltage with a reference voltage to generate the pulse width modulation signal.

Abstract: The present invention discloses a signal transceiving apparatus having echo-canceling mechanism. A mixer circuit includes a Wheatstone bridge and a transformer winding circuit. The Wheatstone bridge includes another transformer winding circuit and a variable load and includes a first input terminal, a first output terminal, a second input terminal and a second output terminal located at each two neighboring arms in an order. A transmission circuit is coupled to the first input terminal and the second input terminal to perform signal transmission through the mixer circuit. A receiving circuit is coupled to the first output terminal and the second output terminal to perform signal receiving through the mixer circuit. A control circuit adjusts the impedance of the variable load when a residual echo noise amount does not satisfy a minimum echo noise amount condition, and stops to adjust the impedance when the residual echo noise amount satisfies the condition.

Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Abstract: Disclosed is a power failure detection device and method capable of issuing a power failure alert early. The device includes a voltage reduction circuit, a detection voltage generating circuit, a detection circuit, and a transmitting circuit. The voltage reduction circuit is or includes at least one active electronic component, and generates an output voltage according to an input voltage higher than the output voltage. The detection voltage generating circuit is coupled between the voltage reduction circuit and a low voltage terminal, and generates a detection voltage according to the output voltage that is between the output voltage and the voltage of the low voltage terminal. The detection circuit generates a detection result according to the detection voltage and a trigger voltage. The transmitting circuit sends a power failure alert to a far-end device on condition that the detection result indicates that the detection voltage is lower than the trigger voltage.

Abstract: A docking station includes a network interface controller (NIC), a dock-side controller and a dock-side connector interface. The NIC is configured to transmit one or more management component transport protocol (MCTP) packets via a system management bus (SMbus). The dock-side controller is electrically coupled to the SMbus, and configured to encode the one or more MCTP packets to one or more vendor specific protocol (VSP) packets. The dock-side connector interface is electrically coupled to the dock-side controller, and configured to transmit the one or more VSP packets to an electrical device to control a basic input output system (BIOS) of the electrical device on the condition that the electrical device is connected to the docking station via the dock-side connector interface.

Abstract: A signal predistortion circuit configuration includes a digital predistortion circuit, a first transceiver, a first analog front-end (AFE) circuit, a second transceiver, and a second AFE circuit. The digital predistortion circuit outputs a first transmission signal according to first predistortion parameters and outputs a second transmission signal according to second predistortion parameters, and the digital predistortion circuit determines whether to adjust the first predistortion parameters according to a first reception signal and determines whether to adjust the second predistortion parameters according to a second reception signal. A transmitting circuit of the first transceiver, the first AFE circuit, and a receiving circuit of the second transceiver jointly generates the first reception signal according to the first transmission signal.

Abstract: An inductor structure includes a first curve metal component, a second curve metal component, a connection component, and a capacitor. The first and the second curve metal components are disposed on a layer. The layer is located at a first plane, the first and the second curve metal components are located at a second plane. The connection component is coupled to the first curve metal component and the second curve metal component. A first terminal of the connection component is coupled to a first terminal of the first curve metal component. A second terminal of the connection component is coupled to a first terminal of the second curve metal component. A first terminal of the capacitor is coupled to a second terminal of the first curve metal component. A second terminal of the capacitor is coupled to a second terminal of the second curve metal component.

Abstract: A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.

Abstract: An inductor device includes a first trace, a second trace, and a double ring inductor. The first trace is disposed at a first area. The second trace is disposed at a second area. The double ring inductor is located at an outside of the first trace and the second trace. The double ring inductor is respectively coupled to the first trace and the second trace in an interlaced manner.

Abstract: The present invention discloses a signal output circuit having anti-interference mechanism. An amplifier is electrically coupled to a power supply and a ground terminal through a first and a second amplifier bond wires, and generates an amplified output signal. A transformer circuit includes a transformer performing impedance transformation on the amplified output signal to generate a transformed output signal and a voltage-stabilizing capacitor suppressing second-order harmonics of the amplifier. A power-terminal side anti-interference circuit includes a power-terminal side bond wire and a power-terminal side anti-interference capacitor. The power-terminal side bond wire is electrically coupled to the ground terminal.

Abstract: A circuit and a method for controlling an audio adapter are provided. The audio adapter includes a button and a microphone, and the microphone is adapted for generating a recorded data. The control circuit includes a button detection circuit, a first-in, first-out (FIFO) data buffer, a USB endpoint buffer, a mute circuit and a USB endpoint control circuit. The button detection circuit is used for detecting whether the button is triggered. The FIFO data buffer is used for storing the recorded data. The USB endpoint buffer is used for storing the recorded data. The mute circuit is used for controlling whether the recorded data is transmitted to the USB endpoint buffer according to whether the button is triggered. The USB endpoint control circuit is used for controlling whether the audio adapter outputs the recorded data according to whether the button is triggered.

Abstract: An inductor device includes a first coil and a second coil. The first coil is wound into a plurality of first circles, and the second coil is wound into a plurality of second circles. At least two of the second circles are interlaced with at least two of the first circles on a first side. The at least two of the second circles are disposed adjacent to each other on the first side. At least one of the first circles is only interlaced with at least one of the second circles on a second side. At least another one of the first circles is only interlaced with at least another one of the second circles on the second side.

Abstract: The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.