Abstract: A stacked inductor device including an 8-shaped inductor structure a stacked coil. The 8-shaped inductor structure includes a first coil and a second coil. The first coil is disposed in a first area. The first coil includes a first sub-coil and a second sub-coil, and the first sub-coil and the second sub-coil are disposed with an interval circularly with each other. The second coil is disposed in a second area, and the second coil is coupled with the first coil on a boundary between the first area and the second area. The second coil includes a third sub-coil and a fourth sub-coil, and the third sub-coil and the fourth sub-coil are disposed with an interval circularly with each other. The stacked coil is coupled to the first coil and the second coil and is stacked partially on or under the first coil and the second coil.

Abstract: A transmitting circuit, which includes a power amplifier, a processing circuit, and a signal strength indicator circuit. The power amplifier is configured to amplify an input signal according to a power gain of the power amplifier to generate an output signal. The processing circuit is configured to adjust the power gain according to an indicating signal. The signal strength indicator circuit has a plurality of power detection ranges. The signal strength indicator circuit is configured to uses one of the plurality of power detection ranges to detect a power of the output signal to generate the indicating signal.

Abstract: A storage device sharing system and a storage device sharing method are provided. The storage device sharing system includes a storage device, a first chip and a second chip. The first chip and the second chip are configured to enter a toggle mode and an arbitration mode. In the toggle mode, the first chip that acts as the master controls the arbitration potential to a first control potential and a second control potential, and communicates with the storage device in response to the arbitration potential being the first control potential, and the second chip that acts as a slave communicates with the storage device in response to the arbitration potential being the second control potential.

Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

Abstract: A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.

Abstract: A detection system and a detection method are provided. The detection method includes: obtaining first, second and third keypoints of a face by a keypoint acquisition module based on an image containing the face, the keypoint acquisition module obtaining the third keypoint based on a predetermined position on a midline of a human face and the first and the second keypoints based on two paired positions outside the midline; obtaining a vector by a first calculation module based on the first and second keypoints; obtaining a two-variable linear function by a second calculation module based on the vector and the third keypoint; and substituting, by a determination module, the coordinates of the first keypoint and the coordinates of the second keypoint into the two-variable linear function to obtain first and second values, respectively, and determining the state of the face based on the first and second values.

Abstract: A detection system and a detection method are provided. The detection method includes: receiving an image containing a face by an angle acquisition module and obtaining a first angle, a second angle and a third angle of the face based on the image; obtaining a first projection value and a second projection value based on the first angle, the second angle and the third angle by a projection calculation module; and performing by a confidence calculation module: performing an exponentiation calculation on the first projection value based on a first correction value to obtain a third value; performing an exponentiation calculation on the second projection value based on a second correction value to obtain a fourth value; and obtaining a confidence value based on the third value and the fourth value.

Abstract: A USB chip includes positive and negative data pins, first and second transceiver circuits, a switching circuit, and a control circuit. During a high-speed handshake stage, the control circuit controls the switching circuit to be in a second state to disconnect the positive and negative data pins from a first terminal impedance circuit and actuates the second transceiver circuit to transmit a second voltage signal via the positive and negative data pins alternately. During a high-speed transmission stage, the control circuit controls the switching circuit to be in a first state to connect the positive and negative data pins with the first terminal impedance circuit and actuates the first transceiver circuit to transmit a first voltage signal, which has a first voltage level lower than a voltage level of the second voltage signal, via the positive and negative data pins alternately.

Abstract: An inductive unit is formed in an integrated circuit. An electromagnetic radiation test is performed thereon. When an amount of electromagnetic radiation exceeds a radiation threshold value, a shielding structure is formed. The shielding structure has a width and a distance separated from the inductive unit such that a decreasing amount of a quality factor of the inductive unit is not larger than a first predetermined value and a shielded amount of electromagnetic radiation is not lower than a second predetermined value. The inductive unit has a symmetric shape and the inductive device further includes a single asymmetric inductive portion. The closed shape of the shielding structure encloses the inductive unit and covers the single asymmetric inductive portion. A part of the single asymmetric inductive portion extends along a peripheral direction of the shielding structure.

Abstract: A timing recovery method includes the following operations: performing a time domain timing recovery process according to a predefined cyclic prefix portion of a first symbol during a downstream time-division duplexing frame period to tune a phase locked loop circuit; and performing a frequency domain timing recovery process according to at least one second symbol that follows the first symbol during the downstream time-division duplexing frame period to tune the phase locked loop circuit.

Abstract: An analog to digital convertor circuit includes an input circuit and a switched capacitor circuit. The input circuit is configured to selectively drain a first current from a first node or drain a second current from a second node according to a first bit and a second bit that have opposite logic values. The switched capacitor circuit is configured to compensate a capacitance value of one of the first node and the second node according to the first bit and the second bit.

Abstract: A processing device includes: a receiving module for receiving a configuration from a control device, wherein the configuration includes a destination address, a length, a filled value and a function type; a control module for (A) configuring an access state for accessing a slave device according to the function type and (B) comparing a counting value with the length to generate a comparison result according to the function type, determining whether data received from the slave device reaches an end to generate a determination result, or both; a reading module for reading the data according to the access state; a writing module for writing the filled value to the destination address according to information of the access state, the determination result and the comparison result; and a transmitting module for transmitting an interrupt signal to the control device according to result(s) of the determination result and the comparison result.

Abstract: The present invention discloses an electronic apparatus operation method having elastic boot file allocation mechanism that includes steps outlined below. A system activation procedure is executed by a processing circuit to load a hard code setting data from a boot code block of a boot data storage circuit to a system storage circuit. Version setting data is loaded to the system storage circuit to replace at least a part of the hard code setting data to generate boot setting data by the processing circuit when the version setting block is determined to include the version setting data by the processing circuit. The system activation procedure is proceeded to be executed according to the boot setting data by the processing circuit.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: A radio frequency receiving circuit includes a first amplification circuit, an oscillation circuit, a frequency mixing and amplification circuit and a dividing circuit. The first amplification circuit is configured to amplify an input signal so as to generate an amplified input signal. The oscillation circuit is configured to provide a local oscillation signal. The frequency mixing and amplification circuit is configured to mix and amplify the amplified input signal according to the local oscillation signal. The dividing circuit is configured to form a dividing loop at a preset frequency for the amplified input signal according to the local oscillation signal when the dividing circuit is driven. A chip including the radio frequency receiving circuit and a main circuit is also provided. The main circuit is configured to drive the dividing circuit when the second input signal is determined to include a signal of the preset frequency.

Abstract: The present invention provides an image processing method, wherein the image processing method includes the steps of: receiving an image signal, wherein the image signal comprises a frame; performing a motion estimation operation on a plurality of blocks within the frame to generate a plurality of first motion vectors, respectively; scaling down the frame to generate a scaled-down frame; performing the motion estimation operation on a specific block within the scaled-down frame to generate a second motion vector corresponding to the specific block; and determining a plurality of final motion vectors of the plurality of blocks of the frame according to the plurality of first motion vectors and the second motion vector.

Abstract: A reference potential generating circuit includes at least one upper-potential selection switch, at least one lower-potential selection switch, a resistor string and at least one multiplexer. Each upper-potential selection switch receives an upper-voltage signal, and one of the upper-potential selection switches is turned on. Each lower-potential selection switch receives a lower-voltage signal, and one of the lower-potential selection switches is turned on. The resistor string is coupled between the upper-potential selection switch and the lower-potential selection switch. The multiplexer includes a plurality of input ends and an output end. The input ends are coupled to ends of the resistors one to one, and the output end of one of the multiplexers outputs a reference potential signal. A control method for the aforementioned reference potential generating circuit is further provided here.

Abstract: A driving circuit for driving a resonant device includes a voltage sensor, a signal controller, a signal generator and a driver. The voltage sensor, coupled to the resonant device, is configured to detect a back electromotive force (EMF) of the resonant device. The signal controller, coupled to the voltage sensor, is configured to control the length of an operation period of the driving circuit according to the back EMF. The signal generator, coupled to the signal controller, is configured to generate a driving signal corresponding to the length of the operation period. The driver, coupled to the signal generator, is configured to output the driving signal to the resonant device.

Abstract: The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.

Abstract: A command transforming method, applied to a command transforming system comprising a first transceiving interface and a second transceiving interface, comprising: receiving at least one command transmitted from a first device via the first transceiving interface; determining a first sequence rule of the first device and a second sequence rule of a second device, wherein the first sequence rule means if the first device is required to process the command in sequence and the second sequence rule means if the second device is required to process the command in sequence; transmitting the command to the second device via the second transceiving interface; processing the command by the second device according to the second sequence rule and transmitting a response corresponding to the command to the second transceiving interface by the second device; and transmitting the response to the first device according to the first sequence rule.