Patents Assigned to Realtek Semiconductor
  • Publication number: 20240292319
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; and a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data. When the first or second Bluetooth member device receives an alert signal, or when a specific ambient sound occurs in the surrounding environment of the first or second Bluetooth member device, the audio broadcasting device utilizes a target control command to instruct the first and second Bluetooth member devices to synchronously reduce their volume to be lower than a predetermined threshold.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 29, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Bi WEI, Yu Hsuan LIU, Chia Chun HUNG
  • Patent number: 12075462
    Abstract: A wireless device includes a time-sensitive queue, an access category queue, a controller, and a transmitter. The access category queue is associated with an access category and a link. The controller is coupled to the access category queue, and is used to acquire a transmission opportunity according to a set of contention parameters of the access category. The transmitter is coupled to the controller and the time-sensitive queue, and is used to when a transmission opportunity is acquired, if the time-sensitive queue contains data, generate a data frame according to the data in the time-sensitive queue, and transmit the data to another wireless device via a link.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: August 27, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Patent number: 12074800
    Abstract: A memory control system includes a front-end circuitry, a back-end circuitry, and a traffic scheduling circuitry. The front-end circuitry is configured to receive a plurality of access requests from a plurality of devices, and adjust an order of the plurality of devices to access a memory according to a plurality of control signals. The traffic scheduling circuitry is configured to generate a plurality of traffic data based on the plurality of access requests and analyze the plurality of traffic data based on a neural network model and a predetermined rule, in order to determine the plurality of control signals. The back-end circuitry is configured to adjust a task schedule of the memory according to the plurality of control signals.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: August 27, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chi-Shao Lai, Hsu-Tung Shih
  • Publication number: 20240284308
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; and a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data. The audio broadcasting device is further arranged to operably utilize a target control command to instruct the first and second Bluetooth member devices to synchronously reduce their volume to be lower than a predetermined threshold.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 22, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Bi WEI, Yu Hsuan LIU, Chia Chun HUNG
  • Publication number: 20240283481
    Abstract: A transceiver and a method for suppressing a harmonic signal in a transceiver are provided. The transceiver includes a transmitter, a compensation circuit, a power combiner, a receiver and a digital baseband circuit. The transmitter outputs a transmitted signal, wherein the transmitted signal includes a main signal having a frequency equal to frf and the harmonic signal having a frequency equal to (N×ff), and N is a non-integer less than one. The compensation circuit outputs a compensation signal having a frequency equal to (N×frf). The power combiner combines the transmitted signal and the compensation signal to generate a combined signal. The receiver receives the combined signal and suppresses the main signal within the combined signal to generate a feedback signal. The digital baseband circuit controls a magnitude of the compensation signal according to a magnitude of the feedback signal.
    Type: Application
    Filed: February 6, 2024
    Publication date: August 22, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventor: Yu-Jung Li
  • Publication number: 20240282302
    Abstract: A watermark-based audio processing method for use in the audio player including a receiver, an analog-to-digital converter, a processor, a digital-to-analog converter and a transmitter includes: the receiver receiving an audio input signal, the analog-to-digital converter converting the audio input signal into a digital input signal including a keyword, the processor detecting an energy of the digital input signal, if the energy exceeds a threshold, the processor determining whether a watermark is included in the digital input signal, if not, the processor embedding the watermark into a predefined digital audio signal to generate a digital output signal, then the digital-to-analog converter converting the digital output signal into an audio output signal, and finally, the transmitter outputting the audio output signal for playback.
    Type: Application
    Filed: January 17, 2024
    Publication date: August 22, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventor: Ying-Ying Chao
  • Publication number: 20240283720
    Abstract: An abnormal recording system and the method for network gateway are related to the abnormal recording system including an external server and a gateway. The gateway includes a network interface, a storage unit, and a processing unit. The processing unit connects to the network interface and the storage unit. The network interface connects to the external server. The storage unit stores an abnormal log file. When the processing unit detects an abnormal status, the processing unit generates the abnormal log file according to the abnormal status, and in the booting state, sends the abnormal log file stored in the storage unit to the external server by the network interface.
    Type: Application
    Filed: May 22, 2023
    Publication date: August 22, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Peng Tang, Xing Zhang
  • Publication number: 20240283405
    Abstract: A bias voltage generating circuit includes a first circuit subunit, a second circuit subunit, and a third circuit subunit. The first circuit subunit is arranged to generate a first bias voltage at a first node in response to a first current and a first input voltage. The second circuit subunit is coupled to the first circuit subunit, and is arranged to receive the first bias voltage and generate a second current flowing through a second node, wherein the second current is mirrored from the first current. The third circuit subunit is coupled to the second node, and is arranged to generate a second bias voltage at a third node in response to the second current and a second input voltage.
    Type: Application
    Filed: January 23, 2024
    Publication date: August 22, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventor: Po-Chih Wang
  • Publication number: 20240284306
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data; and a host device arranged to operably generate and transmit a target control command to the first and second Bluetooth member devices when the first or second Bluetooth member device receives an alert signal, or when a specific ambient sound occurs in the surrounding environment of the first or second Bluetooth member device.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 22, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Bi WEI, Yu Hsuan LIU, Chia Chun HUNG
  • Publication number: 20240284307
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data; and a host device arranged to operably generate and transmit a target control command to the first and second Bluetooth member devices when the host device receives an alert signal, or when a specific ambient sound occurs in the surrounding environment of the host device.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 22, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Bi WEI, Yu Hsuan LIU, Chia Chun HUNG
  • Publication number: 20240284309
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; an audio source device arranged to operably capture a user's voice to generate and transmit corresponding audio signals to the audio broadcasting device; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; and a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data. The audio broadcasting device is further arranged to operably utilize a target control command to instruct the first and second Bluetooth member devices to synchronously reduce their volume to be lower than a predetermined threshold.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 22, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Bi WEI, Yu Hsuan LIU, Chia Chun HUNG
  • Patent number: 12068598
    Abstract: A power supply circuit is configured to supply power to a display panel. The power supply circuit includes a receiver circuit and a transmitter circuit. The receiver circuit is configured to couple the display panel and output a hot plugging signal. The transmitter circuit is configured to receive the hot plugging signal and couple a power circuit. The transmitter circuit is further configured to communicate the receiver circuit to generate an enable signal. The hot plugging signal and the enable signal are configured to control whether a first voltage signal from the power circuit is transmitted to the receiver circuit and the display panel via the transmitter circuit.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: August 20, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Ching-Lan Yang, Zong-Da Huang, Chun-Yuan Huang
  • Patent number: 12068755
    Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: August 20, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsiung Huang, Wei-Cian Hong, Sheng-Yen Shih
  • Patent number: 12066956
    Abstract: A semiconductor device includes a controller circuit and a signal generating circuit. The controller circuit is coupled to a plurality of memory devices and configured to generate a plurality of chip enable signals. One of the chip enable signals is provided to one of the memory devices, so as to respectively enable the corresponding memory device. The signal generating circuit is disposed outside of the controller circuit and configured to receive the chip enable signals and generate a termination circuit enable signal according to the chip enable signals. The termination circuit enable signal is provided to the memory devices. When a state of any of the chip enable signals is set to an enabled state, a state of the termination circuit enable signal generated by the signal generating circuit is set to an enabled state.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: August 20, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventor: Tsan-Lin Chen
  • Patent number: 12068753
    Abstract: The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: August 20, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yun-Tse Chen, Hsuan-Ting Ho, Liang-Wei Huang, Tzung-Hua Tsai
  • Patent number: 12068740
    Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a second capacitor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled to a reference voltage through the third switch and the sixth switch, coupled to the input voltage through the fifth switch, and coupled to the control terminal of the first transistor through the fourth switch.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: August 20, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yen-Ting Wu
  • Publication number: 20240273887
    Abstract: A neural network system and a signal processing method are provided. The neural network system includes at least one processing unit and a neural network module. The signal processing method includes: inputting a neural network input to the neural network module by the processing unit to generate an input at a previous layer of each convolutional transformer layer; performing pointwise convolution on the input by a key embedding layer based on key convolutional kernels to output a key tensor; performing convolution on the input by a value embedding layer based on value convolutional kernels to output a value tensor; performing a convolution on the cascading tensor of a first tensor and the key tensor by an attention embedding layer based on attention convolution kernels to output an attention tensor; and outputting an output tensor based on the attention tensor and the value tensor by an output module.
    Type: Application
    Filed: June 29, 2023
    Publication date: August 15, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chih-Wei Wu, Chien-Hao Chen, Wei-Hsiang Shen, Shih-Tse Chen
  • Publication number: 20240273944
    Abstract: A training system, a training method, and a recognition system are provided. The training method is used to train a neural network module including: an encoder module, a shared decoder module, a synthesis module, and a classification module. The training method includes performing in a training epoch: repeatedly executing: taking a training image from a training set as an input image, obtaining a first loss based on training feature images of the training image and the feature images corresponding to the training image, and obtaining a second loss based on a classification marker of the training image and a classification generated by the classification module in correspondence with the training image; and updating first parameters and second parameters based on an average value of all the first losses and an average value of all the second losses obtained in the preceding step and an update algorithm.
    Type: Application
    Filed: August 21, 2023
    Publication date: August 15, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chien-Hao Chen, Chih-Wei Wu, Shih-Tse Chen
  • Publication number: 20240275284
    Abstract: A switching regulator is arranged to receive an input voltage to generate an output voltage, and includes an inductor, a mode selection circuit, a multiplexer, and a driving circuit. The mode selection circuit is arranged to generate a selection signal, wherein the selection signal indicates whether the switching regulator operates in a PWM mode or a PFM mode. The multiplexer is arranged to output a PWM signal or a PFM signal according to the selection signal. The driving circuit is arranged to generate a driving signal according to the PWM/PFM signal to control switches in the switching regulator. In response to the switching regulator operating in the PFM mode, an energy storage time of the inductor in one cycle of the PFM signal is generated according to a period length of the PWM signal.
    Type: Application
    Filed: February 6, 2024
    Publication date: August 15, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventor: Chien-Hao Chiu
  • Patent number: 12062598
    Abstract: An integrated circuit lead frame and a semiconductor device thereof are provided. The integrated circuit lead frame includes a die pad and a plurality of leads. The die pad is provided to attach a die. The plurality of leads are provided for connection to the die through wire bonding. The leads include a pair of a first lead and a second lead. The first lead includes a first body and a first extension portion connected to the first body. The second lead includes a second body and a second extension portion connected to the second body. The first extension portion and the second extension portion extend in directions toward each other.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: August 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu-Hsin Wang, Nai-Jen Hsuan