Abstract: A distribution network system and method. The distribution system has a plurality of communication channels and is connected to a mesh network. The mesh network uses one of the plurality of communication channels as a distributable network channel. The distribution network system includes an already-distributed network node and a to-be-distributed network node. The already-distributed network node is located in the mesh network and is configured to broadcast a mesh network beacon to the distributable network channel. The to-be-distributed node is configured to alternately monitor whether the mesh network beacon is detected on each communication channel.

Abstract: An operation method is implemented by a receiver device. The operation method includes following steps: detecting a signal on a transmission line; performing a channel estimation to acquire a length of the transmission line; comparing the length with at least one length threshold value to generate a comparison result; and adjusting a depth of a FIFO process according to the comparison result.

Abstract: The present invention discloses a data decoding circuit. A data reforming circuit receives encoded data encoded by using tail-biting convolutional code to identify a first unknown bit section, a known bit section and a second unknown bit section in an order to further connect the second unknown bit section and the first unknown bit section in series to generate data to be decoded. A decoding circuit decodes the data to be decoded by using Viterbi algorithm and at least one piece of known bit information to generate a decoded result that includes a second decoded bit section and a first decoded bit section respectively corresponding to the second unknown bit section and the first unknown bit section. A data restoring circuit connects the first decoded bit section, a known decoded bit section corresponding to the known bit section and the second decoded bit section in series to generate decoded data.

Abstract: A signal processing device includes a decision feedback equalizer and a coefficient adjusting circuit. The decision feedback equalizer includes a first equalizer configured to perform filtering on a first signal according to a set of first coefficients to generate a first filtered signal. The set of first coefficients includes multiple first coefficients. The coefficient adjusting circuit is configured to adaptively adjust one or more of the first coefficients according to an error signal. A limit operation of the first coefficients is selectively performed. When the limit operation of the first coefficients is performed, at least one of the first coefficients is set to a first predetermined value to generate a set of limited first coefficients.

Abstract: A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether an error exists in the plurality of scan chains or not according to the plurality of scan output data by a decoding circuit.

Abstract: A bridge chip with a function of expanding external devices and an associated expansion method are provided, wherein the bridge chip may include at least one transmission interface, a bridge control unit and a connecting port. The transmission interface may be configured to make at least one external device outside the bridge chip couple to the bridge chip; the bridge control unit is coupled to the transmission interface, and may be configured to control priority of the external device for performing data transmission; and the connecting port is coupled to the bridge control unit, and may be configured to make the bridge chip couple to a host device, to allow the host device to perform data transmission with the external device. More particularly, a number of the external device is expandable.

Abstract: A communication system includes a medium access control circuit and at least one physical layer circuit. The at least one physical layer circuit is coupled to the medium access control circuit. The medium access control circuit sends a control command to the at least one physical layer circuit via a SERDES interface. In response to the control command, the at least one physical layer circuit sends physical layer data to the medium access control circuit via the SERDES interface.

Abstract: A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.

Abstract: A transmission circuit includes a data input pin, a serial-to-parallel converter, an interface decoder, a parallel-to-serial converter, and a processor circuit. The serial-to-parallel converter is electrically coupled to the data input pin. The serial-to-parallel converter converts a plurality of data signals received by the first data input pin into a set of parallel data signals. The interface decoder is electrically coupled to the serial-to-parallel converter. The interface decoder decodes the set of parallel data signals to generate a set of decoded data signals for parallel transmission. The parallel-to-serial converter is electrically coupled to the interface decoder. The parallel-to-serial converter converts the set of decoded data signals into a plurality of input data signals for serial transmission. The processor circuit is electrically coupled to the parallel-to-serial converter. The processor circuit receives and processes the plurality of input data signals.

Abstract: A signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive first partial data of output data from a data generation unit, convert the first partial data of the output data into a first transmission signal correspondingly, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least second partial data of the output data and convert the at least second partial data of the output data into at least one second transmission signal correspondingly, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Abstract: A network data prediction method applied to a device that implements an OSI model is provided. The device communicates with a target network device that implements the OSI model. The method includes the following steps: generating a transmission data according to a communication protocol of a first abstraction layer, the transmission data being able to be processed by a first peer abstraction layer of the target network device, and the first peer abstraction layer corresponding to the first abstraction layer and obeying the communication protocol; generating a predicted data according to the communication protocol and the transmission data; and transmitting the transmission data and the predicted data to a second abstraction layer.

Abstract: A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.

Abstract: A method of controlling a multi-antenna communication system includes: obtaining a first baseband signal through a first antenna; performing a cross-correlation calculation on the first baseband signal and default information during a period of time, thereby to obtain a plurality of cross-correlation calculation results; calculating energy of the first baseband signal to obtain a first energy value; determining connectivity state of the first antenna according to the first energy value and the cross-correlation calculation results; and controlling a signal processing circuit of the multi-antenna communication system according to the connectivity state of the first antenna.

Abstract: Disclosed is a method for a USB power receiving device selecting a power supply option. The method is performed by the USB power receiving device and includes: receiving N power data object(s) (PDO(s)) from a USB power supplying device, in which the N is a positive integer; checking whether at least one of M PDO(s) of the USB power receiving device matches at least one of the N PDO(s) according to a selection rule including a voltage requirement and a current-related requirement and accordingly generating a request data object (RDO), in which the M is a positive integer; and transmitting the RDO to the USB power supplying device to request the USB power supplying device to supply power to the USB power receiving device according to the RDO.

Abstract: A method for electrostatic discharge protection in a receiver and associated receiver are provided. The receiver includes a reference voltage terminal, a detection terminal, at least one set of receiving terminals and at least one set of termination resistors. The method includes: according to a voltage level of the detection terminal, generating a detection result; and according to the detection result, controlling whether to configure said at least one set of termination resistors to be respectively coupled between said at least one set of receiving terminals and the reference voltage terminal.

Abstract: A negative feedback system architecture and a loop filter thereof are provided. The negative feedback system architecture includes a loop filter, a pulse width modulation circuit, and a driver. The loop filter includes a three-stage series integrator for receiving a signal and outputting the filtered signal. The loop filter has three in-bandwidth poles and at least two in-bandwidth zeros. The pulse width modulation circuit is electrically connected to the loop filter for receiving the filtered signal and modulating it into a pulse width modulation signal to output. The driver is electrically connected to the pulse width modulation circuit and the loop filter for receiving the pulse width modulation signal to generate an output signal to drive a load device, and the output signal is fed back to the loop filter.

Abstract: An error handling method for a transmission interface connecting between a first device and a second device for performing data transmission between the first device and the second device, wherein a connection type between the transmission interface and the first device is a direct interface (DI) and the connection type between the transmission interface and the second device is an indirect interface (II), and the error handling method comprises: when an error is detected at the direct interface, reporting an error event to a host of the first device; when an error is detected at the indirect interface, attempting to handle the error without letting the host discover it; and when the error detected at the indirect interface is determined as unable to be solved, reporting another error event to the host.

Abstract: A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.

Abstract: The electronic device with power-off partition includes a signal transmitting module, two repeater modules, and a working module. Each of the repeater modules includes a first power domain, a second power domain, and a transceiver circuit. A transmission path between the first power domain and the second power domain is maintained at a logic state when the second power domain is in power off mode. The transceiver circuit of one of the two repeater modules encodes a standby signal obtained from the signal transmitting module and transmits an encoded standby signal. The transceiver circuit of the other of the repeater modules decodes the encoded standby signal and transmits a decoded standby signal. The working module transmits, according to the decoded standby signal, a power-off signal to the transceiver circuits of the two repeater modules, so that the second power domains enter the power-off mode in response to the power-off signal.

Abstract: A split-type display system includes a processing device, a display device, and a transmission cable connecting the processing device and the displaying device. The processing device includes a processing unit, a first and a second conversion unit. The display device includes a third and a fourth conversion unit, and a display unit. The processing unit generates a first image signal and a first timing control signal. The first and the second conversion units, respectively, converts the first image signal and the first timing control signal into a second image signal and a second timing control signal. The third and the fourth conversion units, respectively, receive and convert the second image signal and the second timing control signal into a third image signal and a third timing control signal. The display unit displays the third image signal according to the third timing control signal.