Abstract: A video transmission system includes a first processing circuit and a second processing circuit. The first processing circuit is configured to output a composite video signal. The composite video signal includes a video area, an extension area, and an edge area. The extension area stores a non-video signal. The second processing circuit is configured to receive the composite video signal and extract the non-video signal from the composite video signal.

Abstract: A split-type display system includes a processing device, a display device, and a transmission cable connecting the devices. The processing device includes a processing unit and a low-to-high unit. The processing unit generates a first image signal having both a first transmission rate and a first channel number. The low-to-high unit converts the first image signal into a second image signal having both a second transmission rate and a second channel number. The first transmission rate is lower than the second transmission rate. The display device includes a high-to-low unit and a display unit. The high-to-low unit receives and converts the second image signal into a third image signal having both a third transmission rate and a third channel number. The display unit displays the third image signal. a number of channels of the transmission cable is the same as the second channel number.

Abstract: A calculation method using pixel-channel shuffle convolutional neural network is provided. In the method, an operating system receives original input data. The original input data is pre-processed by a pixel shuffle process to be separated into multiple groups in order to minimize dimension of the data. The multiple groups of data are then processed by a channel shuffle process so as to form multiple groups of new input data selected for convolution operation. The unselected data are abandoned. Therefore, the dimension of the input data can be much effectively minimized. A multiplier-accumulator of the operating system is used to execute convolution operation using a convolution kernel and the multiple new groups of input data. Multiple output data are then produced.

Abstract: A test system includes a transmitter, capacitor, and receiver. The transmitter includes: an output circuit coupled to the receiver via the capacitor; a transmitting circuit transmitting a predetermined signal to a pad of the output circuit during a first test; a signal generator outputting a first signal and second signal to the pad during a first process and second process of a second test; and a comparator comparing the pad's signal with a reference signal in the first process and second process to determine whether the second test passes. The receiver includes: an input circuit coupled to the transmitter via the capacitor; a switch coupled between the input circuit and a receiving circuit to be conducting in the first test and second process and nonconducting in the first process; and the receiving circuit determining whether the first test passes according to the predetermined signal and assisting the capacitor in discharging.

Abstract: A communication device is disclosed. The communication device includes a transceiver circuit, an echo canceler, and a processor. The transceiver circuit is configured to transmit a test signal to a channel. The echo canceler is configured to obtain a plurality of echo power of a reflected signal corresponding to the test signal. The processor is configured to obtain a plurality of positions on the channel according to a parameter value. The parameter value is N, a number of the plurality of positions is N, and the plurality of positions corresponds to the top N largest of the plurality of echo power. The echo canceler is further configured to eliminate part of the plurality of echo power corresponding to the plurality of positions according to the plurality of positions.

Abstract: A filter includes multiple filter circuits. The filter circuits are coupled in series between an input terminal and an output terminal, to generate an output signal according to an input signal. One of the filter circuits operates as an active filter circuit or a passive filter circuit according to amplitude of the input signal.

Abstract: An audio device is adapted to receive and process a digital audio signal and output an analog audio signal. The audio device includes an adder, a digital-to-analog conversion circuit, an amplifying circuit, a voltage detecting circuit and an offset compensating circuit. The voltage detecting circuit detects a supply voltage received by the amplifying circuit. The offset compensating circuit generates a DC offset compensation value according to the supply voltage. The adder adds the digital audio signal and the DC offset compensation value to output an added signal. The digital-to-analog conversion circuit converts the added signal into a converted analog audio signal. The amplifying circuit amplifies the converted analog signal to output an amplified analog signal. Accordingly, the audio device can reduce pop noise caused by a DC offset.

Abstract: A voltage modulation circuit includes a charge pump circuit and a voltage detection circuit. The voltage detection circuit is coupled to the charge pump circuit. Herein, the charge pump circuit supports a plurality of power supply modes with different conversion rates and is configured to perform a power supply operation in a selected power supply mode of the power supply modes according to a control signal, to convert a power supply voltage into at least one output voltage, and to output a wake-up signal when switching of the selected power supply mode meets a specific condition. The voltage detection circuit is activated by the wake-up signal, and is configured to detect the output voltage and to suspend the power supply operation of the charge pump circuit according to a magnitude of the output voltage.

Abstract: A bit rate control method includes the following operations: receiving a first target bit of a video to be coded; determining a second target bit for first coding tree units (CTUs) in CTUs of the video according to the first target bit; determining a fourth target bit of at least one fourth CTU in the CTUs according to an actual bit of at least one second CTU in the CTUs and a third target bit of at least one third CTU in the CTUs, in which the at least one second CTU is completely coded, the at least one third CTU is not completely coded, and a coding of the at least one fourth CTU is not started; and sequentially adjusting at least one coding parameter for coding the video according to the second target bit, the third target bit, and the fourth target bit.

Abstract: A method of foreground auto-calibrating data reception window for a DRAM system is disclosed. The method comprises receiving data strobe and data from a DRAM of the DARM system, capturing a data strobe clock according to the received data strobe, generating three time points with a period of the data strobe clock, sampling the data at the three time points, to obtain three sampled data, determining whether to adjust positions of the three time points according to a comparison among the three sampled data, and configuring the valid data reception window according to the positions of the three time points when determining not to adjust the positions of the three time points.

Abstract: A method and image processing circuit for performing searching operations regarding an image are provided, wherein the image includes a plurality of blocks. The method includes: utilizing a grouping circuit to divide the plurality of blocks into a plurality of groups, wherein a group within the plurality of groups corresponds to a searching region within a target image, the group includes NB reference blocks within the plurality of blocks, the searching region includes NB sub-regions, and NB is an integer greater than one; utilizing a searching circuit to search for the NB reference blocks in the NB sub-regions, respectively, to generate NB searching results respectively corresponding to the NB reference blocks; and utilizing a selecting circuit to select a searching result from the NB searching results, for utilizing the searching result to represent a portion or all of the NB searching results.

Abstract: An encoding method for a wireless local area network includes encoding a packet via a cyclic coding scheme into a first amount of multiple first blocks; processing each of the first amount of the first blocks into a second amount of multiple second blocks; and encoding the second amount of the second blocks via a block coding scheme.

Abstract: A chip includes a receiving, a transmission, a control, and a switch circuit. The receiving circuit is operated at a first voltage and receives a first data. The transmission circuit is operated at the first voltage. Under general mode, the control circuit is operated at a second voltage and generates a second data to the transmission circuit according to the first data. The control circuit includes a first clock source configured to provide a first clock under general mode. The control circuit is operated according to the first clock. Under general mode, the switch circuit is operated at the first voltage, and controls the second voltage to pause the second voltage supplying to the control circuit to enter sleep mode. Under sleep mode, the switch circuit controls the supply of the second voltage to the control circuit according to the first data to return to general mode.

Abstract: A method and a system for controlling data response with the aid of at least one attribute of a transaction identifier (ID) are provided. The method includes: transmitting the at least one attribute in conjunction with the transaction ID from any master device within one or more master devices to a slave device; and according to the at least one attribute, determining whether to utilize a specific data path among multiple data paths for sending response data corresponding to the transaction ID from a memory device within the slave device to the aforementioned master device. More particularly, the specific data path is a data path having maximum transmission efficiency among the multiple data paths.

Abstract: Inductor-capacitor oscillators and common mode resonators are provided. The inductor-capacitor oscillator includes a first transistor, a second transistor, an inductor, a first capacitor, a second capacitor, a first winding, and a second winding. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal and a sixth terminal. The first, second and third terminals are electrically connected to the fifth, fourth and sixth terminals, respectively. The first capacitor and the inductor are coupled between the first terminal and the fourth terminal. The second capacitor is coupled between the third terminal and a reference voltage. The first winding is coupled between the third terminal and the reference voltage. The second winding is coupled between the third terminal and the reference voltage. The first winding and the second winding are symmetric to each other.

Abstract: A motion image integration method includes acquiring a raw image, detecting a first motion region image and a second motion region image by using a motion detector according to the raw image, merging the first motion region image with the second motion region image for generating a motion object image according to a relative position between the first motion region image and the second motion region image, and cropping the raw image to generate a sub-image corresponding to the motion object image according to the motion object image. A range of the motion object image is greater than or equal to a total range of the first motion region image and the second motion region image. Shapes of the first motion region image, the second motion region image, and the motion object image are polygonal shapes.

Abstract: A clock distribution network includes receiving a remote voltage signal; transmitting the remote voltage signal into a local voltage signal using a current-mode transmission scheme that comprises a cascade of a voltage-to-current driver, a transmission line, a current buffer, and a LC (inductor-capacitor) tank; transmitting the local voltage signal into a first destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a first capacitively driven wire and a first inverter buffer; and transmitting the local voltage signal into a second destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a second capacitively driven wire and a second inverter buffer.

Abstract: A video program playing device implements a video program shielding method. The video program shielding method includes receiving a video program signal and predetermined age information, and obtaining video program information from the video program signal; determining, according to the video program information, whether the video program signal matches the predetermined age information; determining whether at least one target meeting the predetermined age information is detected within a predetermined range of a video program playing device; and stopping outputting the video program signal when the video program signal fails to match the predetermined age information and the at least one target is detected.

Abstract: The present invention provides a signal transmission method for data transmission through an audio transmission interface. The method includes: receiving audio data and first control data that is generated based on at least one first human-machine interaction; packing the audio data into at least one first data unit; packing the first control data into at least one second data unit; and transmitting a bit stream including the first data unit and the second data unit at a transmission rate that is higher than a sampling rate of the audio data.

Abstract: An Ethernet power sourcing equipment (PSE) and a power management method thereof are provided. The Ethernet PSE includes a plurality of ports and a controller. Each port is coupled to a powered device (PD), to supply power to the PD through the port when the PD is in a power supply stage. When the PD enters a startup stage before the power supply stage, the controller calculates a remaining power quota based on a power quota allocated to the PD.