Abstract: A control device and a circuit board are provided. The control device can cooperate with the circuit board, and includes a ball grid array. The ball grid array includes a plurality of power balls and a plurality of ground balls, which are jointly arranged in a ball region. The power balls and the ground balls are respectively divided into a plurality of power ball groups and a plurality of ground ball groups. One of the ground ball groups includes two ground balls and is adjacent to a power ball group. A ball pitch between the two ground balls is greater than that between one of the power balls and one of the ground balls adjacent to each other. The circuit board includes a contact pad array corresponding to the ball grid array of the control device so that the control device can be disposed on the circuit board.

Abstract: A dual-mode signal amplifying circuit includes: a first and a second input terminals for receiving differential input signals; two output terminals for providing differential output signals; a first through a third current sources; a first switch positioned between the first current source and a first node, and controlled by the first input terminal; a second switch positioned between the first current source and a second node, and controlled by the second input terminal; a third switch positioned between the first node and a fixed-voltage terminal, and controlled by a third node; a fourth switch positioned between the second node and a fixed-voltage terminal and controlled by the third node; a fifth switch positioned between the second current source and a fixed-voltage terminal, and controlled by the first node; and a sixth switch positioned between the third current source and a fixed-voltage terminal, and controlled by the second node.

Abstract: Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Abstract: A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.

Abstract: A method and a control chip for performing access control of a memory device are provided, wherein the control chip is coupled to a host device. The method includes: utilizing a first transmission interface of the control chip to determine whether the memory device supports a second transmission interface different from the first transmission interface to generate a determination result; and according to user permissions of a user regarding the host device, determining whether to allow the control chip to decide whether to utilize the second transmission interface to access the memory device based on the determination result. In addition, if the user permissions satisfy a predetermined condition, a user interface of the host device may display a pop-up window in order to allow the user to decide which one of the first transmission interface and the second transmission interface to utilize for accessing the memory device.

Abstract: A temperature computing parameter providing circuit, configured to generate sensing voltage values and calibrated voltage values as temperature computing parameters for a target electronic device, including: a parameter computing circuit, configured to compute a reference voltage, which is a cross voltage of a reference resistor coupled to the target electronic device in series, to generate a reference voltage value, and to compute the sensing voltage, which is a cross voltage of the target electronic device, to generate the sensing voltage value; a reference temperature sensing circuit, configured to sense a current reference temperature of the reference resistor; and a computing circuit, configured to calibrate the reference voltage value to generate the calibrated voltage value according to a calibrating function and the current reference temperature. The calibrating function corresponds to a resistance-temperature variation function.

Abstract: A processing method of a customized key based on an Android platform includes receiving a key value of an input key, mapping the key value to a key scan code, identifying a to-be-blocked key according to the key scan code, converting, when the input key is the to-be-blocked key, the key scan code into a specific key code by a key block module, and sending, by bypassing an Android framework layer by the key block module, the specific key code to an application program for processing.

Abstract: A current generation circuit includes a temperature sensing circuit, a resistor element having a resistance, and a current mirror circuit. The temperature sensing circuit is configured to generate a reference voltage having corresponding magnitude according to a temperature of the current generation circuit. The resistor element is coupled with the temperature sensing circuit, and is configured to determine magnitude of a reference current according to the reference voltage and the resistance. The current mirror circuit is coupled with the temperature sensing circuit, and is configured to generate an output current according to the reference current. The temperature sensing circuit and the resistor element both have positive temperature coefficients or negative temperature coefficients.

Abstract: A communication system is provided, which includes a power amplifier, a receive-end filter, an ADC, an output simulation circuit, and a predistortion circuit. The power amplifier amplifies a RF input signal to generate a RF output signal. The RF input signal is generated according to a baseband signal. The receive-end filter filters a feedback signal generated according to the RF output signal to output a filtered feedback signal. A bandwidth of the filtered feedback signal is at least 3 to 5 times a bandwidth of the RF input signal. The ADC converts the filtered feedback signal to a digital input signal. The output simulation circuit generates, according to the digital input signal and the baseband signal, a reference signal simulating the RF output signal. The predistortion circuit builds a predistortion model according to the reference signal.

Abstract: The invention provides a USB device and a data transfer method thereof. The USB device is coupled to a host and transfers at least one packet to the host. The USB device includes a memory, a USB controller, and a transfer management circuit. The memory stores packets. The USB controller is configured to transfer the packets to the host. The transfer management circuit is coupled between the memory and the USB controller and configured to sequentially read the packets from the memory and sequentially transfer the packets to the USB controller, and to perform the following operations: ending the data transfer when a stored content of the memory does not meet a condition for continuing packet transfer; or ending the data transfer when a last transferred packet meets a preset condition and a next packet that follows the last transferred packet does not meet the preset condition.

Abstract: A multiplexer device includes a plurality of selection circuits and potential setting circuits. The plurality of selection circuits respectively receive a first data signal and a second data signal, and select a corresponding one of the first data signal and the second data signal as an output signal according to the first selection signal. When the second data signal is selected as the output signal, the potential setting circuit sets a potential of a node of a first selection circuit of the plurality of selection circuits to a first voltage. The first selection circuit is configured to receive a first data signal.

Abstract: A signal processing method for maintaining a signal relative relationship and an electronic device thereof are provided. The signal processing method includes: detecting that a current input period of a vertical synchronization signal changes relative to a previous input period; determining whether a frequency difference between a pulse width modulation signal and the vertical synchronization signal is within an acceptable range, and when the frequency difference is not within the acceptable range, performing a frequency adjustment stage to adjust a period of the pulse width modulation signal to be close to the current input period; selectively performing a phase adjustment stage to adjust a phase of the pulse width modulation signal to a phase of the vertical synchronization signal; and maintaining a relative phase relationship between the pulse width modulation signal and the vertical synchronization signal.

Abstract: A signal transmission device is provided, including a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. A first positive differential pin of the plurality of positive differential pins transmits a positive signal content of a first differential signal. A second positive differential pin transmits a positive signal content of a second differential signal. A first negative differential pin of the plurality of negative differential pins transmits a negative signal content of the first differential signal. A second negative differential pin transmits a negative signal content of the second differential signal. The first positive differential pin and the first negative differential pin are located on one side of a first ground pin, and the second positive differential pin and the second negative differential pin are located on the other side.

Abstract: The present disclosure discloses a signal equalization apparatus. A channel length estimation circuit determines a transmission channel length of the input signal such that a processing circuit retrieves predetermined feed-forward equalizer coefficients. A feed-forward equalizer equalizes the input signal according to operation feed-forward equalizer coefficients. An auto gain circuit amplifies the input signal according to an offset signal. A signal adding circuit adds the amplified input signal and a feedback adjusting signal to generate an added input signal. A data slicer generates a data-slicing result and the offset signal according to reference thresholds based on the added input signal. A feedback equalizer equalizes the data-slicing result to generate the feedback adjusting signal according to operation feedback equalizer coefficients.

Abstract: The application discloses a router coupled to a first device and a second device. The router includes a first packet input interface, a second packet input interface, a first register, a second register, a control circuit and a switch module. The switch module includes a control port, a first packet output interface and a second packet output interface. The application further discloses a routing method. The router and routing method saves idle time and improves quality of service.

Abstract: The present disclosure discloses an image data transmission apparatus having synchronous data transmission mechanism. Output stage circuits respectively receive and store image data corresponding to a part of a display frame. A primary switch circuit is coupled to a primary output stage circuit of the output stage circuits so as to maintain a control voltage of a control terminal at a first level when a primary frame aligning signal having the latest timing is not received from the primary output stage circuit, and switches the control voltage to a second level when the primary frame aligning signal is received. The output stage circuits output the image data to an image data receiving apparatus to display the display frame synchronously when the output stage circuits receive the control voltage having the second level through voltage transmission paths having the same signal transmission time.

Abstract: An electronic component for an electronic device with a locking function and an unlocking method thereof are provided. The unlocking method includes: receiving a first sound extraction request by a first processing circuit when the electronic device is in a locked mode; determining, by the first processing circuit, whether a first voice input signal is received after receiving the first sound extraction request; determining, by the first processing circuit when the first processing circuit receives the first voice input signal, whether first voice data included in the first voice input signal matches first preset voice data; and transmitting, by the first processing circuit, the first voice input signal to the second processing circuit when the first voice data matches the first preset voice data, to trigger the second processing circuit to determine whether second voice data included in the first voice input signal matches second preset voice data.

Abstract: An image processing chip test method comprising: controlling a power supply circuit to provide a first operating voltage to an image processing chip comprising a storage device; and when reading written first image data from the storage device, the test device receives a first error detection code corresponding to the first image data and determines whether the first error detection code means an error occurs. If an error occurs, record the first operating voltage as an erroneous operating voltage, and if the error does not occur, provide a second operating voltage to the image processing chip. Also, when the written second image data is read from the storage device, the test device receives a second error detection code corresponding to the second image data and determines whether the second error detection code means an error occurs.

Abstract: A method and a system for pixel channel imbalance compensation for an image sensing circuit are provided. The system includes an image acquisition circuit having a lens, a color filter and an image sensor and a processing circuit. In the method performed by the processing circuit, a second frame image is retrieved from a motion image, and a first frame image that has undergone noise reduction can be retrieved from a memory. Motion detection is performed between the frames by comparing the first frame image and the second frame image. The motion detection is referred to as a reference for determining how to perform 3D noise reduction. A compensation value for channel imbalance between the adjacent channels can be estimated based on the image under noise reduction in a same buffer. While the pixel channel imbalance is compensated, the image is then restored by an interpolation method.

Abstract: A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.