Abstract: A docking station for power management includes an integrated circuit, a first signal input/output (I/O) port, a network interface controller, and a first controller. The first signal I/O port is connected to a host controller of a host. When the host enters a sleep mode or a standby mode, the network interface controller is disconnected, or there is no network packet transmission, the integrated circuit cuts off a signal connection between the integrated circuit and the first signal I/O port, so that the host controller enters a deepest sleep state. When the network interface controller receives a wake-on-LAN signal, the network interface controller informs the first controller through a function pin, and the first controller wakes up the host controller through the first signal I/O port. The network interface controller controls, in response to the wake-on-LAN signal, the integrated circuit to re-establish the signal connection.

Abstract: A data transceiver device and an operation method are provided. The data transceiver device receives input data and transmits output data. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal according to the set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data according to an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and the state of the buffer circuit.

Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

Abstract: A signal processing device includes an echo estimation device, a captured signal buffer device and a delay estimation device. The echo estimation device generates an echo estimation signal according to a reference signal and a set of reflection path simulation coefficients and compensates the echo estimation signal according to a first delay to generate a compensated echo estimation signal. The captured signal buffer device buffers a captured signal captured by microphone device and outputs the captured signal according to a second delay to generate a compensated captured signal. The delay estimation device estimates an amount of delay adjustment according to the compensated echo estimation signal and the compensated captured signal and updates the first delay or the second delay according to the amount of delay adjustment. A difference between an upper bound and a lower bound of the first delay is smaller than or equal to 1.

Abstract: A data processing device includes decoder circuits, a checker circuit, and a control circuit. The decoder circuits set groups of first sampling points and groups of second sampling points according to an initial transition edge of a first signal, and perform a parallel decoding on the first signal according to the groups of first sampling points and the groups of second sampling points, in order to generate a second signal and a third signal. The checker circuit checks the second signal and the third signal, in order to generate a check result. The control circuit selects at least one of the decoder circuits according to the check result for receiving subsequent data.

Abstract: The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.

Abstract: A signal processing method including the steps of: using a FFT window to process a last symbol of a first sub-frame of a frame to generate a frequency-domain signal, wherein the FFT window has a first start point; performing an IFFT operation on the frequency-domain signal to generate a channel impulse response; performing a channel estimation on the channel impulse response to generate a channel profile; referring to the channel profile of the last symbol of the first sub-frame, an attribute of a start symbol of a second sub-frame and the first FFT window start point to determine a second FFT window start point; using the FFT window having the second start point to process the start symbol of the second sub-frame to generate another frequency-domain signal.

Abstract: A quadrature clock generator includes a variable delay clock generator configured to receive a first clock and a third clock and output a second clock and a fourth clock in accordance with a control signal, wherein the first clock and the third clock are substantially the same but offset in timing by one half of the period; a quadrature phase error detector configured to receive the first clock, the second clock, the third clock, and the fourth clock and output a first phase detection signal and a second phase detection signal, wherein the first phase detection signal represents a relative timing between the first clock and the second clock and the second phase detection signal represents a relative timing between the second clock and the third clock; and an amplifier configured to amplify a difference between the first phase detection signal and the second phase detection signal into the control signal.

Abstract: A network switch and a network switch system thereof are provided. The network switch includes a plurality of connection ports and a processing circuit. When any of the connection ports receives a first abnormal message packet and one of the connection ports is in a disabled state, the processing circuit sets the connection port in the disabled state to switch to an enabled state, and the processing circuit does not forward the first abnormal message packet in the single loop network. When one of the connection ports is abnormal and each of the connection ports forming the single loop network is in the enabled state, the processing circuit sets the abnormal connection port to switch to the disabled state, and transmits a second abnormal message packet to other network switches in the single loop network through another connection port that is not abnormal.

Abstract: A voice wake-up apparatus used in an electronic device that includes a voice activity detection circuit, a storage circuit and a smart detection circuit is provided. The voice activity detection circuit receives an input sound signal and detects a voice activity section of the input sound signal. The storage circuit stores a predetermined voice sample. The smart detection circuit receives the input sound signal to perform a time domain and a frequency domain detection on the voice activity section to generate a syllable and frequency characteristic detection result, compare the syllable and frequency characteristic detection result with the predetermined voice sample and generate a wake-up signal to a processing circuit of the electronic device when the syllable and frequency characteristic detection result matches the predetermined voice sample to wake up the processing circuit.

Abstract: A multimedia streaming and network apparatus that includes a network module, a storage module and a multi-core processing module is provided. The multi-core processing module performs network communication through the network module and executes the hypervisor from the storage module to perform a multimedia streaming and network apparatus operation method that includes the steps outlined below. A virtual system is established. A router virtual machine is established in the virtual system to execute a router operating system configured to perform a network routing function. A multimedia streaming virtual machine is established in the virtual system to execute a multimedia streaming operating system configured to perform a multimedia playback function. The router virtual machine receives a multimedia network stream and transmits the multimedia stream through a bridge of the virtual system to be playback by the multimedia virtual machine.

Abstract: A skin color image gamut weight detecting method and a device thereof are provided. The method includes: receiving an image including first color components and second color components; obtaining a skin color region, a skin color category, and a first gamut; obtaining first color component values and first cardinal numbers according to the first color components; obtaining second color component values and a plurality of second cardinal numbers according to the second color components; obtaining a second gamut and a weight center according to the skin color category, the first cardinal numbers, the second cardinal numbers, the first color component values, and the second color component values; obtaining a first weight area and a second weight area according to the first gamut and the second gamut; and obtaining a skin color gamut weight map according to the weight center, the first weight area, and the second weight area.

Abstract: A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.

Abstract: A decoding circuit and a decoding method based on the Viterbi algorithm are provided. The decoding method includes the following steps: decoding an encoded data based on the Viterbi algorithm to generate a decoded data; performing error correction on the decoded data to obtain a data content of the encoded data; comparing the decoded data and the data content to generate bit correction information; using the encoded data to calculate multiple first branch metrics based on the Viterbi algorithm, the first branch metrics corresponding to a target bit of the data content; adjusting at least one of the first branch metrics based on the data content and the bit correction information to generate multiple second branch metrics; and selecting the first branch metrics or the second branch metrics based on the bit correction information.

Abstract: A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

Abstract: A symbol boundary detection method includes: calculating desired signal power according to a receiving signal by a receiver device; calculating interference power according to the receiving signal by the receiver device; calculating a signal-to-interference power ratio according to the desired signal power and the interference power by the receiver device; finding a best signal-to-interference power ratio to determine a reference symbol boundary time by the receiver device; and processing the receiving signal according to the reference symbol boundary time by the receiver device for a subsequent demodulation process performed by a demodulator circuit.

Abstract: The present invention provides a pin multiplexer including a multiplexing circuit, a control circuit and a detecting circuit. The multiplexing circuit includes a first port, a second port and a third port, wherein the first port, the second port and the third port are coupled to a first device, a second device and a third device, respectively. The control circuit is configured to control the multiplexing circuit to operate in a first mode or a second mode, wherein when the multiplexing circuit operates in the first mode, the first port is coupled the second port; and when the multiplexing circuit operates in the second mode, the first port is coupled to the third port. When operating in the second mode, the detecting circuit detects a signal of the first port to generate a detection result for dynamically switching the data transmission direction between the third device and the first device.

Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.

Abstract: Disclosed is a payload mapper including N mapper(s), each of which includes a controller, multiple mapping circuits, an output control circuit, and a storage circuit. The controller includes: a decoding circuit receiving a first-format signal and decoding at least a part of this signal to find out the type of a control signal relating to the first-format signal; and a conversion control circuit generating a selecting signal according to the type of the control signal to choose one of the mapping circuits. The mapping circuits receive the first-format signal and selecting signal, and the selected mapping circuit converts the first-format signal into a second-format signal according to the selecting signal. The output control circuit is coupled to the mapping circuits and outputs at least a part of the second-format signal as an effective output signal. The storage circuit temporarily stores the effective output signal and then outputs it.

Abstract: A wireless communication device and a dynamic anti-interference method for the same are provided. The device includes at least two wireless communication circuits. When the method operates in the wireless communication device, the device monitors activities of every wireless communication circuit through a clear channel assessment method for acquiring signal strength of every wireless communication circuit. The assessment allows the device to perform a corresponding anti-interference measure for each of the wireless communication circuits. For example, when the device acknowledges that a second wireless communication circuit of the device starts to work as a first wireless communication circuit transmits or receives signals, the device controls a receiver or a transmitter of the second wireless communication circuit to perform an anti-interference measure such as a gain control for a receiver or power adjustment for a transmitter.