Patents Assigned to Realtek Semiconductor
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Patent number: 11070207Abstract: A bootstrapped switch is provided. The bootstrapped switch includes a first transistor, a second transistor, a capacitor and five switches. The first transistor receives an input voltage and outputs an output voltage. A first terminal of the second transistor receives the input voltage, and a second terminal of the second transistor is coupled to a first terminal of the capacitor. In a first clock phase, the capacitor is being charged. In a second clock phase, the control terminal of the first transistor and the control terminal of the second transistor are substantially equipotential with a second terminal of the capacitor. The control terminal of the first transistor and the control terminal of the second transistor are coupled to the power supply voltage within a predetermined time before the terminal of the first clock phase or within a predetermined time after the start of the second clock phase.Type: GrantFiled: October 5, 2020Date of Patent: July 20, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Shih-Hsiung Huang
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Publication number: 20210216127Abstract: A chip includes an instruction storage unit, a processor core, an input circuit, a neural network circuit, power-consuming circuits, and a switch circuit. When the chip runs, the processor core performs a processing operation according to the instructions under being supplied with a current. At the same time, the neural network circuit predicts an upcoming change of the current according to data stream, representing the time-varying current, from the input circuit, and outputs a corresponding control signal. The switch circuit selectively provides a clock to one or more power-consuming circuits under the control of the control signal, so that each power-consuming circuit receiving the clock operates under being supplied with the current. Therefore, the chip can predict upcoming requirement of high electricity consumption, and duly start up a current wasting mechanism in advance, to avoid an excessive voltage drop without affecting operation efficiency of the processor core.Type: ApplicationFiled: May 19, 2020Publication date: July 15, 2021Applicant: REALTEK SEMICONDUCTOR CORP.Inventor: Kuo-Chao Lin
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Patent number: 11062429Abstract: A denoising method based on a signal-to-noise ratio (SNR), which includes: obtaining a current input coefficient; obtaining a current noise standard deviation by querying a first relationship table; querying a second relationship table according to the current noise standard deviation and the current input coefficient to obtain a current slope corresponding to the current input coefficient; generating a current output coefficient by multiplying the current input coefficient and a compression magnification function; and calculating the current output coefficient by substituting the current noise standard deviation, the current input coefficient, and the current slope.Type: GrantFiled: January 22, 2020Date of Patent: July 13, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Wan-Ju Tang, Tsung-Hsuan Li, Shih-Tse Chen
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Patent number: 11063628Abstract: A communication device capable of echo cancellation includes a digital circuit, a transmitter circuit, a hybrid circuit, an adjustable capacitor circuit, and a receiver circuit. The digital circuit transmits a digital transmission signal and receives a digital reception signal. The transmitter circuit outputs an analog transmission differential signal according to the digital transmission signal. The hybrid circuit outputs a transmission signal to an external circuit via an adjustable capacitor circuit according to the analog transmission differential signal, and outputs an analog reception differential signal to a receiver circuit according to at least one of the analog transmission differential signal and a reception signal from the external circuit. The adjustable capacitor circuit controls a delay difference between positive-end and negative-end signals of the transmission signal according to an echo cancellation control signal.Type: GrantFiled: June 1, 2020Date of Patent: July 13, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Liang-Wei Huang, Yu-Xuan Huang
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Patent number: 11061073Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.Type: GrantFiled: December 3, 2019Date of Patent: July 13, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ying-Yen Chen, Jeong-Fa Sheu, Chia-Jui Yang, Po-Lin Chen
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Patent number: 11063624Abstract: A communication device is adapted to perform a communication method. The communication method includes: initializing a link between the communication device and a corresponding device; responding to a being-trained procedure to obtain a being-trained log; and sending a training command string according to the being-trained log. Therefore, the corresponding device adjusts its transmission characteristic according to the received training command string to reach appropriate interoperability between devices.Type: GrantFiled: March 30, 2020Date of Patent: July 13, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chih-Hung Huang
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Patent number: 11061072Abstract: A system chip, and a built-in self-test circuit and a self-test method thereof are provided. The system chip includes an analog front end circuit, a digital physical layer circuit and a built-in self-test circuit. The digital physical layer circuit is coupled to the analog front end circuit, and the built-in self-test circuit is coupled to the digital physical layer circuit and is arranged to test the analog front end circuit with aid of the digital physical layer circuit.Type: GrantFiled: May 16, 2019Date of Patent: July 13, 2021Assignee: Realtek Semiconductor Corp.Inventors: I-Hsueh Lin, Chia-Min Liu
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Patent number: 11057694Abstract: The present invention provides a wireless earphone, wherein the wireless earphone includes a first pin, a microprocessor and a power management unit, the first pin is arranged to connect to an external charging device, the microprocessor includes a core circuit and a wakeup circuit coupled to the first pin, and the power management unit includes an uninterruptible power area for providing a power to the wakeup circuit. In the operations of the wireless earphone, when the core circuit is at a sleep mode, if the wakeup circuit detects that a voltage level of the first pin changes, the wakeup circuit generates a wakeup signal to wake up the core circuit.Type: GrantFiled: August 15, 2019Date of Patent: July 6, 2021Assignee: Realtek Semiconductor Corp.Inventor: Chih-Hsiang Shen
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Patent number: 11055061Abstract: A signal transmission method and a circuit structure for heterogeneous platforms are provided. The method includes: adjusting signal transmission bandwidths between a first platform and a bridge circuit and between the bridge circuit and a second platform according to signal transmission speeds between the first platform and the bridge circuit and between the bridge circuit and the second platform; transmitting a command signal from the first platform to the bridge circuit and saving the command signal at a buffer of the bridge circuit; reading the command signal at the buffer of the bridge circuit by the second platform; transmitting data to the buffer of the bridge according to the command signal by the second platform; acquiring the data at the buffer of the bridge by the first platform.Type: GrantFiled: October 10, 2019Date of Patent: July 6, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Sa-Chia Ho, Hong-Chang Wu, Hsin-Chen Chen, Yi-Hsuan Wu
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Patent number: 11057027Abstract: The present invention provides a circuit having a plurality of modes, wherein the circuit includes a first circuit, a second circuit, a first multiplexer, a second multiplexer and a specific flip-flop. In the operations of the circuit, the first circuit is configured to generate a first signal, the second circuit is configured to generate a second signal, the first multiplexer is configured to output one of the first signal and the second signal according to a mode selection signal, the second multiplexer is configured to output one of a first clock signal and a second clock signal according to the mode selection signal, and the specific flip-flop is configured to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal.Type: GrantFiled: July 21, 2020Date of Patent: July 6, 2021Assignee: Realtek Semiconductor Corp.Inventor: Szu-Yang Chang
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Patent number: 11057123Abstract: The application discloses a transceiver and a transceiver calibration method. The transceiver includes: a calibration signal generation unit for generating a first test signal and a second test signal to a transmission unit in a gain calibration mode; the transmission unit for generating a combined signal according to the first test signal, the second test signal and a transmission gain; a mixer for performing self-mixing upon the combined signal to generate a self-mixed signal; a receiving unit for generating a receiving signal according to the self-mixed signal; a Fourier transformer for computing a power of the receiving signal at a specific frequency; and a gain calibration unit for adjusting the transmission gain according to the power at the specific frequency in the gain calibration mode.Type: GrantFiled: July 9, 2020Date of Patent: July 6, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yuan-Shuo Chang, Tzu Ming Kao
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Patent number: 11055467Abstract: A method for performing power mesh optimization with the aid of additional wires and an associated apparatus are provided. The method includes: reading a clock cell definition file to obtain respective basic information of a plurality of clock cells in a circuit design; and according to the respective basic information of the plurality of clock cells, executing a power mesh optimization procedure, including: regarding any type of clock cells in multiple types of clock cells within the plurality of clock cells, classifying the clock cells into a plurality of sub-types according to respective sizes of the type of clock cells; and performing power mesh enhancement on respective clock cells of a set of sub-types within the plurality of sub-types, to add a set of additional wires crossing a set of original wires in an original power mesh at each clock cell of any sub-type of the set of sub-types.Type: GrantFiled: May 18, 2020Date of Patent: July 6, 2021Assignee: Realtek Semiconductor Corp.Inventors: Chien-Cheng Liu, Yun-Chih Chang
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Patent number: 11057070Abstract: A signal receiving device adapting to a signal input mode and a signal processing method for the same are provided. The signal receiving device can determine various signal input modes, such as a differential signal or a single-ended signal, and select an appropriate signal source, such that the signal receiving device can not only receive the input signal correctly, but also adjust the received input signal to a differential signal with the same amplitude and opposite phases to make subsequent data analysis work easier.Type: GrantFiled: October 14, 2020Date of Patent: July 6, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chen-Kang Lin, Hung-Yi Chang, Bing-Juo Chuang
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Patent number: 11057064Abstract: A Radio Frequency Interference (RFI) estimation device for generating an estimated RFI signal includes a combiner, a first multiplier and a second multiplier. The combiner is configured to combine a first digital signal and a second signal to generate the estimated RFI signal. The first multiplier is configured to generate the first digital signal according to an in-phase signal and a first cosine signal. The second multiplier is configured to generate the second digital signal according to a quadrature-phase signal and a first sine signal. The first cosine signal and the first sine signal are generated based on a frequency and the in-phase signal and the quadrature-phase signal are generated based on the frequency and one or more harmonics of the frequency.Type: GrantFiled: September 16, 2020Date of Patent: July 6, 2021Assignee: Realtek Semiconductor Corp.Inventors: Chi-Hsi Su, Liang-Wei Huang
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Patent number: 11057042Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.Type: GrantFiled: March 12, 2020Date of Patent: July 6, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chih-Chieh Yang, Shih-Hsiung Huang, Liang-Huan Lei
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Patent number: 11055255Abstract: An interface connection apparatus disposed in a first electronic device is provided that includes an analog physical layer circuit, a waveform generation circuit and a media access control circuit. The analog physical layer circuit receives an analog handshake signal from a second electronic device and generates a digital handshake signal. The waveform generation circuit determines whether a matching times that a pulse parameter of each of pulses included in the digital handshake signal is within a predetermined pulse parameter range reaches predetermine times and generates a digital output signal when the matching times reaches the predetermine times, and an output pulse parameter of all output pulses of the digital output signal is within the predetermined pulse parameter range. The media access control circuit determines that the analog handshake signal is valid when the media access control circuit receives the digital output signal to keep performing handshake.Type: GrantFiled: January 14, 2020Date of Patent: July 6, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Fu-Ching Hsu, Chih-Wei Chang
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Patent number: 11057675Abstract: A media streaming device is provided that includes a media streaming module, a super capacitor and a protection module. The media streaming module provides the media stream. The super capacitor has a first terminal coupled to a power-supplying path and a second terminal coupled to a ground terminal. The protection module includes a current limiter and a disabling unit. The current limiter receives a power signal and performs current-limiting to generate a fixed-current power to charge the super capacitor and supply power to the media streaming module through the power-supplying path. The current limiter further detects a voltage of the first terminal of the super capacitor. The disabling unit disables the media streaming module when the voltage of the first terminal of the super capacitor is not higher than a voltage threshold value, and enables the media streaming module when the voltage is higher than the voltage threshold value.Type: GrantFiled: December 4, 2018Date of Patent: July 6, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chao-Min Lai, Chien-Liang Chen
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Patent number: 11048651Abstract: A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.Type: GrantFiled: January 16, 2020Date of Patent: June 29, 2021Assignee: Realtek Semiconductor Corp.Inventors: Ching-Sheng Cheng, Wen-Wei Lin, Kuan-Chia Huang
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Patent number: 11050396Abstract: An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.Type: GrantFiled: July 23, 2019Date of Patent: June 29, 2021Assignee: Realtek Semiconductor Corp.Inventors: Yu-Ting Chung, Shawn Min, Yi-Chun Hsieh
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Patent number: 11050805Abstract: A method for controlling a stream buffer in a media playback device includes: receiving a data stream from a download buffer of the media playback device at a processing rate; buffering the data stream in the stream buffer at a buffering rate; performing a pre-parsing operation on the data stream buffered in the stream buffer to obtain a pre-parsed result; and selectively adjusting at least one of the processing rate and the buffering rate according to the pre-parsed result.Type: GrantFiled: December 4, 2019Date of Patent: June 29, 2021Assignee: Realtek Semiconductor Corp.Inventor: Chun-Yi Chen