Abstract: An audio codec circuit includes a voltage detecting circuit, an output processing circuit, a digital-to-analog conversion circuit, and an audio amplifying circuit. The voltage detecting circuit is configured to detect an input voltage of an input power. The output processing circuit obtains a first output compensation value according to the input voltage, an output circuit parameter, and a first output spec. The output processing circuit processes a digital audio and compensates the processed audio by the first output compensation value. The digital-to-analog conversion circuit is configured to perform digital-to-analog conversion on the compensated audio to obtain an analog audio. The audio amplifying circuit is configured to amplify the analog audio and output the amplified audio.

Abstract: A method for dynamically limiting a memory bandwidth of a graphics processing unit (GPU) is applicable to a bandwidth-limited system. The bandwidth-limited system includes an audio/video decoder and a GPU. The method includes detecting a plurality of decoding times of a plurality of frames of an audio/video decoded by an audio/video decoder, and adjusting a max grant amount of a memory bandwidth of a GPU according to the plurality of decoding times of the plurality of frames and a target time. Therefore, in the case where the total memory bandwidth is limited, the memory bandwidth of the GPU is limited by the performance of the corresponding audio/video decoder such that, during audio/video playback, the effect of audio/video playback can be prevented from being affected and at the same time a better graphical user interface can be provided.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC receives an analog input signal and generates a digital code. The ADC includes a sigma-delta modulator (SDM), a decimation filter and a detection circuit. The SDM includes a loop filter, a quantizer and a digital-to-analog converter (DAC). The loop filter receives the analog input signal. The quantizer is coupled to the loop filter and quantizes an output of the loop filter to generate a digital output signal. The DAC is coupled to the quantizer and the loop filter. The decimation filter is coupled to the SDM and converts the digital output signal into the digital code. The detection circuit is coupled to the SDM and detects a node voltage of the SDM and generate a control signal. The control signal is utilized to control the loop filter, the quantizer, a feedback path of the SDM and/or a feedforward path of the SDM.

Abstract: The present invention provides a receiving circuit applied to an HDMI, wherein the receiving circuit includes a decoder, a frame key calculating circuit, a line key calculating circuit and a control circuit. In the operations of the receiving circuit, the decoder decodes a data stream to generate at least one image frame, the frame key calculating circuit is arranged to calculate a frame key according to the image frame, the line key calculating circuit is arranged to calculate a plurality of line keys according to the image frame, and the control circuit determines to turn off or turn on the line key calculating circuit according to whether or not the image frame is displayed on a display panel.

Abstract: A multimedia streaming and network apparatus is provided that includes a router module, a storage module and a processing module for executing the application program in the storage module to perform the multimedia streaming and network apparatus operation method. A first streaming request packet corresponding to a physical STB is received through a LAN port. A multicast and hardware offload function corresponding to the LAN port is activated. A STB virtual machine is operated to perform a STB function. A second streaming request packet corresponding to the STB virtual machine is received. A multicast and hardware offload function corresponding to the processing module port is activated. A video stream from a remote server is transmitted by the router module through the LAN port and the processing module port respectively to the physical STB and the STB virtual machine to be processed and playback.

Abstract: A switching circuit includes a live wire power obtaining circuit, a control circuit, and a tunable capacitor array. The live wire power obtaining circuit is coupled to a live wire to receive an alternating current (AC) voltage. The control circuit is configured to perform a zero-crossing detection to the alternating current voltage. The tunable capacitor array is coupled to the live wire power obtaining circuit and the control circuit. The control circuit is configured to control the live wire power obtaining circuit to supply power to the control circuit or the tunable capacitor array to discharge to supply power to the control circuit based on a state of a first switch and a zero-crossing detection result.

Abstract: A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal.

Abstract: A clock and data recovery apparatus is provided that includes a sampling circuit, a storage circuit and a determining circuit. The sampling circuit includes sampling units each sampling a received data according to one of reference clock signals to generate a sampling result. The storage circuit includes FIFO storage units configured to store the sampling result of the received data corresponding to different time spots. The determining circuit is configured to set a certain number of received data as a reference data pattern, to adjust a starting position of a sampling window according to a transition point of sampled values within the reference data pattern when only one data transition exists therein and adjust a length of the sampling window according to an amount of high state sample points of the sampled values within the reference data pattern when more than one data transitions exist therein.

Abstract: An image adjusting method includes: detecting objects in an input image and classifying the objects through a deep learning model, thereby obtaining at least one category included in the input image, a weight value corresponding to each of the categories, and at least one block of the input image corresponding to each of the categories; obtaining a color information and a coordinate information of each of the blocks; and adjusting at least one of the sharpness, dynamic contrast control (DCC), and independent color management (ICM) of each of the block of the input image according to the weight value, the coordinate information, and the color information corresponding to each of the blocks, thereby generating an output image.

Abstract: A display control method having dynamic backlight adjusting mechanism is provided that includes the steps outlined below. A backlight control signal having a backlight period that is 1/N times of a Vsync period of a Vsync signal is generated. A first Vsync period end time after the Vsync period switches from a first period length to a second period length is calculated. A first backlight period end time after the first Vsync period end time is determined as a transition period start time. A time difference between the transition period start time and the first Vsync period end time is calculated. A transition period length between the second period length and the time difference is calculated and divided into interval lengths each equals to a third period length. The backlight control signal operated to have the third period length is generated within the transition period.

Abstract: A transceiver circuit includes a transceiver antenna, a transmitter circuit, a receiver circuit, a frequency synthesizer and a baseband circuit. The transmitter circuit transmits a radio frequency signal corresponding to a radio frequency through the transceiver antenna. The frequency synthesizer provides a first local oscillation signal and a second local oscillation signal having a first local oscillation frequency and a second local oscillation frequency, respectively. The baseband circuit operates in a transmitting mode and a receiving mode. In the transmitting mode, the frequency synthesizer provides the first local oscillation signal, and in the receiving mode, the frequency synthesizer provides the second local oscillation signal, the first local oscillation frequency is a non-integer multiple of the radio frequency, and the second local oscillation frequency is an integer multiple of the radio frequency.

Abstract: A video transmission method and a system thereof are provided. The video transmission method includes: obtaining a first display timing setting parameter of one or more display devices. A total transmission bandwidth of the display device is calculated according to the first display timing setting parameter, and when the total transmission bandwidth is greater than a maximum transmission bandwidth between a video source and a conversion device, a second display timing setting parameter with a lower bandwidth is generated corresponding to the first display timing setting parameter. The video source transmits a video signal conforming to the second display timing setting parameter to the conversion device. The conversion device converts the second display timing setting parameter of the video signal back to the first display timing setting parameter. The video signal conforming to the first display timing setting parameter is transmitted to the corresponding display device.

Abstract: A transmitting-end Bluetooth device includes: a transmitting-end Bluetooth transceiver circuit; a packet generating circuit, coupled with the transmitting-end Bluetooth transceiver circuit; and a transmitting-end control circuit, coupled with the transmitting-end Bluetooth transceiver circuit and the packet generating circuit, arranged to operably instruct the packet generating circuit to insert an auto-pairing request and a source Bluetooth device address into one or more target packets when the transmitting-end Bluetooth device initiates a Bluetooth auto-pairing procedure, and arranged to operably control the transmitting-end Bluetooth transceiver circuit to transmit the one or more target packets when the transmitting-end Bluetooth device operates under a predetermined transmitting-end operating mode, so that a receiving-end Bluetooth device operating under a predetermined receiving-end operating mode is enabled to actively conduct a Bluetooth auto-pairing procedure with the transmitting-end Bluetooth devi

Abstract: Disclosed are a color reconstruction device and method capable of accurately recovering the missing color of a target pixel. The device includes: a direction-characteristic estimation circuit calculating a horizontal-variation characteristic and a vertical-variation characteristic according to a first color of a target pixel and the values of pixels within a reference range, in which the target pixel is in the reference range and a current value of the target pixel is a first color value; an edge-texture decision circuit determining which of N predetermined relations matches the relation between the horizontal-variation characteristic and the vertical-variation characteristic and thereby determining the directional characteristic of the target pixel, in which the N is not less than four; and a color recovery circuit calculating a second and a third color values of the target pixel according to the directional characteristic and the values of the pixels within the reference range.

Abstract: A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Abstract: An integrated oscillator includes a first inductor laid out as a first loop and a second inductor laid out as a second loop; a first capacitor laid out between two ends of the first loop; a second capacitor laid out between two ends of the second loop; a third inductor, a fourth inductor, a third capacitor, and a fourth capacitor that are laid out inside the first loop; and a cross-coupling transistor pair configured to electrically cross couple the two ends of the first loop and also the two ends of the second loop. The whole structure is substantially symmetrical with respect to a plane of symmetry.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A differential transimpedance amplifier includes a first pair of common-gate amplifiers having a first NMOS transistor and a second NMOS transistor configured in a cross-coupling topology using a first capacitor and a second capacitor, a second pair of common-gate amplifiers comprising a first PMOS transistor and a second PMOS transistor configured in a cross-coupling topology using a third capacitor and a fourth capacitor, wherein an output of the first pair of common-gate amplifiers and an output of the second pair of common-gate amplifiers are coupled via a fifth capacitor and a sixth capacitor.

Abstract: A negative feedback system architecture and a loop filter thereof are provided. The negative feedback system architecture includes a loop filter, a pulse width modulation circuit, and a driver. The loop filter includes a three-stage series integrator for receiving a signal and outputting the filtered signal. The loop filter has three in-bandwidth poles and at least two in-bandwidth zeros. The pulse width modulation circuit is electrically connected to the loop filter for receiving the filtered signal and modulating it into a pulse width modulation signal to output. The driver is electrically connected to the pulse width modulation circuit and the loop filter for receiving the pulse width modulation signal to generate an output signal to drive a load device, and the output signal is fed back to the loop filter.

Abstract: The present invention discloses a direction-finding chip, a direction-finding method and a beacon. The direction-finding chip is applied to a beacon of a direction-finding system. The beacon includes multiple antennas and an inertial measurement unit (IMU). A mobile device can calculate angle information according to supplement provided by the beacon. The direction-finding chip includes a computation circuit and a radio frequency circuit. The computation circuit generates coordinate conversion information or a correction amount of the coordinate conversion information according to an acceleration and a magnetic field vector generated by the IMU. The coordinate conversion information or the correction amount can be used to compensate the angle information. The radio frequency circuit is coupled to the computation circuit and configured to transmit the supplement and the coordinate conversion information or the correction amount.