Abstract: A video transmission method and a system thereof are provided. The video transmission method includes: obtaining a first display timing setting parameter of one or more display devices. A total transmission bandwidth of the display device is calculated according to the first display timing setting parameter, and when the total transmission bandwidth is greater than a maximum transmission bandwidth between a video source and a conversion device, a second display timing setting parameter with a lower bandwidth is generated corresponding to the first display timing setting parameter. The video source transmits a video signal conforming to the second display timing setting parameter to the conversion device. The conversion device converts the second display timing setting parameter of the video signal back to the first display timing setting parameter. The video signal conforming to the first display timing setting parameter is transmitted to the corresponding display device.

Abstract: A multi-member Bluetooth device for communicating data with a source Bluetooth device, wherein the source Bluetooth device acts as a master in a first piconet. The multi-member Bluetooth device includes a main Bluetooth circuit and an auxiliary Bluetooth circuit. The main Bluetooth circuit acts as a slave in the first piconet, and acts as a master in a second piconet. The auxiliary Bluetooth circuit acts as a slave in the second piconet. The main Bluetooth circuit generates a first slave clock and a second main clock synchronized with a first main clock generated by the source Bluetooth device, and samples a first audio data to be playback. The auxiliary Bluetooth circuit generates a second slave clock and a third slave clock synchronized with the second main clock, and samples a second audio data to be playback.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates a command reference clock signal. Each of the access signal transmission circuits adjusts a phase and a duty cycle of one of access signals from a memory access controller according to the command reference clock signal to generate one of output access signal including an output external read enable signal to activate a memory device and an output internal read enable signal. The data reading circuit samples a data signal from the activated memory device according to a sampling signal to generate and transmit a read data signal to the memory access controller. The multiplexer generates the sampling signal according to the output internal read enable signal under a SDR mode and generates the sampling signal according to a data strobe signal from the activated memory device under a DDR mode.

Abstract: A multi-member Bluetooth device for communicating data with a remote Bluetooth device is disclosed including: a main Bluetooth circuit and an auxiliary Bluetooth circuit. In the period during which the auxiliary Bluetooth circuit operates at a relay mode, the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device, and the auxiliary Bluetooth circuit does not sniff packets transmitted from the remote Bluetooth device. But the auxiliary Bluetooth circuit switches from the relay mode to a sniffing mode if the data type of packets transmitted from the remote Bluetooth device changes. In the period during which the auxiliary Bluetooth circuit operates at the sniffing mode, the auxiliary Bluetooth circuit sniffs packets issued from the remote Bluetooth device while the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device.

Abstract: A sigma-delta analog-to-digital converter includes: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing the output signal from the subtractor to generate a filtered signal; a signal comparing circuit for selectively operating in an offset detection mode or a signal comparison mode, wherein the signal comparing circuit generates an error signal irrelevant to the relative magnitude between the filtered signal and a reference signal in the offset detection mode, and generates a comparison signal corresponding to the relative magnitude between the filtered signal and the reference signal in the signal comparison mode; an offset calibration control circuit for calibrating the offset of the signal comparing circuit and for controlling the signal comparing circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter for generating the feedback signal according to the comparison signal.

Abstract: A signal calibration method that includes the steps outlined below is provided. A phase of an under-test signal generated by a memory controller is set to initiate a calibration process. A low-power status control command is issued by transmitting signals that include the under-test signal generated by the memory controller to a memory unit to switch the memory unit to a low power status, the low-power status control command forcing the under-test signal to toggle. A read command is issued by the memory controller to the memory unit for reading data. When the responded data does not match the predetermined data, the phase of the under-test signal is determined to be within a timing margin by the memory controller. When the responded data matches the predetermined data, the phase of the under-test signal is determined to be not within the timing margin by the memory controller.

Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Abstract: A main Bluetooth circuit and an auxiliary Bluetooth circuit of a multi-member Bluetooth device for communicating data with a remote Bluetooth device are disclosed. In the period during which the auxiliary Bluetooth circuit operates at a relay mode, the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device, and the auxiliary Bluetooth circuit does not sniff packets transmitted from the remote Bluetooth device. But the auxiliary Bluetooth circuit switches from the relay mode to a sniffing mode if the data type of packets transmitted from the remote Bluetooth device changes. In the period during which the auxiliary Bluetooth circuit operates at the sniffing mode, the auxiliary Bluetooth circuit sniffs packets issued from the remote Bluetooth device while the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device.

Abstract: Disclosed is a duty cycle corrector including a buffer circuit, an upper circuit, and a lower circuit. The buffer circuit includes: a first buffer circuit receiving a first input signal and thereby outputting a second output signal to a second output terminal; a second buffer circuit receiving a second input signal and thereby outputting a first output signal to a first output terminal; and a latch circuit coupled between the first and second output terminals. The upper circuit is coupled between a high voltage terminal and the buffer circuit and transmits current to the first and second output terminals according to each of the first and second input signals. The lower circuit is coupled between the buffer circuit and a low voltage terminal and withdraws current flowing through the first and second output terminals according to each of the first and second input signals.

Abstract: The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.

Abstract: A temperature adaptive audio amplifier device includes a digital analog convertor, a gain controller, an amplifier, a temperature sensor and a decision circuit. The digital analog convertor transforms a digital audio signal into an analog convertor. The gain controller includes a gain value and is configured to perform gain processing on the analog audio signal and generate a gained analog audio signal. The amplifier is configured to amplify the gained analog audio signal and generates an amplified analog audio signal. The temperature sensor generates a temperature detect signal according to a junction temperature of the amplifier. The decision circuit receives the temperature detect signal and generates an adaptive gain adjustment signal to the gain controller. The adaptive gain adjustment signal is used to adjust the junction temperature of the amplifier to be within an upper temperature threshold and a lower temperature threshold.

Abstract: A circuit that includes an input stage circuit and an output stage circuit is provided. The input stage circuit includes a differential pair circuit and two output current mirror circuits. The differential pair circuit operates according to a first voltage source to receive a first and a second input voltages and generate a first and a second output currents. The two output current mirror circuits operate according to a second voltage source to generate a first current mirror output current fed to an input stage output node according to the first output current and generate a second current mirror output current flowed from the input stage output node according to the second output current. The output stage circuit operates according to the second voltage source to receive an input voltage from the input stage output node to generate an output voltage.

Abstract: Disclosed is a capacitive touch detecting device including a sampler circuit and a detection-and-calibration circuit. The sampler circuit executes the following steps: charging a capacitor when the level of a clock signal is high, wherein the capacitor's capacitance is a first capacitance provided a touch event occurs and is a second capacitance provided the touch event doesn't occur, the first capacitance is greater than the second capacitance and related to a parasitic capacitance and a touch capacitance, and the second capacitance is unrelated to the touch capacitance; sampling a voltage determined by the capacitor during the level transition of the clock signal to generate a sample value; and discharging the capacitor when the level of the clock signal is low. The detection-and-calibration circuit determines whether the touch event occurs and whether at least one parameter needs to be updated according to the sample value and at least one parameter.

Abstract: A frequency doubler includes a multiplexer, a digitally controlled delay circuit, a divide-by-two circuit, a duty cycle detector, and a controller. The multiplexer receives a first clock and output a second clock in accordance with a third clock, in which the first clock has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase. The digitally controlled delay circuit receives the second clock and outputs a fourth clock in accordance with a digital word. The divide-by-two circuit receives the fourth clock and outputs the third clock. The duty cycle detector receives the second clock and outputs a logical signal in accordance with a comparison of a duty cycle of the second clock with a target duty cycle value. The controller outputs the digital word in accordance with the logical signal.

Abstract: A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.

Abstract: A boot image cloud deployment system and method are provided. The system includes an electronic device and a server. The server includes a storage medium and a control circuit. The electronic device is configured to issue a request instruction. The storage medium is configured to store a plurality of boot images. Each boot image includes a plurality of object files, and a combination sequence of the object files of each boot image is different from a combination sequence of the object files of the other boot images. The control circuit is configured to send back one of the boot images to the electronic device according to the request instruction. The electronic device executes the received boot image.

Abstract: An inductor is laid out on a multi-layer structure, the inductor having a multi-turn coil including a plurality of metal traces laid out on at least two metal layers and a plurality of vias configured to provide inter-layer connection, wherein the multi-turn coil includes a first half configured to conduct a current flow between a first end and a center tap and a second half configured to conduct a current flow between a second end and the center tap; and an additional metal laid out on a metal layer below a lowest metal layer of the multi-turn coil, wherein the additional metal is laid out beneath the first half if the second half has a greater parasitic capacitance, or alternatively beneath the second half if the first half has a greater parasitic capacitance.

Abstract: A transmission interface communicating method used in a display device that includes the steps outlined below is provided. A first status update signal is received from a host device to turn a hot plug detect (HPD) status of the display device to a high status. A HPD signal having a low status is transmitted to the host device in response to the first status update signal. A configuration signal is received from the host device. A configuration acknowledgement signal is transmitted to the host device in response to the configuration signal. The HPD signal having the high status is actively transmitted to the host device.

Abstract: The present invention provides an image adjustment method and associated image processing circuit for performing the following operations upon each pixel of an image: obtaining R, G, B values and infrared ray (IR) value corresponding to the current pixel; generating multiple initial compensation parameters corresponding to the R, G, B values; generating an over-compensation parameter according to the R, G, B and IR values; comparing the over-compensation parameter with at least one threshold value to generate a compensation adjustment coefficient; and performing IR crosstalk compensation upon the image with the compensation adjustment coefficient.

Abstract: A main Bluetooth circuit of a multi-member Bluetooth device includes: a Bluetooth communication circuit; a data transmission circuit; and a control circuit arranged to operably conduct bidirectional packet transmission with a remote Bluetooth device through the Bluetooth communication circuit by utilizing a Bluetooth wireless transmission approach, and arranged to operably communicate data with other devices through the data transmission circuit. During the period in which the Bluetooth communication circuit conducts packet transmission with the remote Bluetooth device, an auxiliary Bluetooth circuit of the multi-member Bluetooth device sniffs packets transmitted from the remote Bluetooth device.