Abstract: A circuit includes an input impedance, an operational amplifier, a voltage-adjusting circuit, a pulse-generating circuit, and a drive circuit. The input impedance is coupled to an input terminal of the operational amplifier, receives an input voltage, and outputs an input current. The operational amplifier is coupled to a first power voltage and outputs an amplified signal according to an input operating voltage and a feedback signal. The voltage-adjusting circuit adjusts the input operating voltage of the operational amplifier. The pulse-generating circuit generates a pulse width modulation signal according to the amplified signal. The drive circuit is coupled to a second power voltage and generates a driving signal according to the pulse width modulation signal. The feedback signal is correlated with the driving signal.

Abstract: A circuit includes a core circuit configured to receive an input clock and output and output clock in accordance with a control signal, the core circuit having an encoder configured to encode the control signal into a plurality of control words and a plurality of duty cycle correction buffers configured in a cascade topology and controlled by said plurality of control words, respectively; a duty cycle detection circuit configured to output a logical signal in accordance with a comparison of a duty cycle of the output clock with a target value; and a controller configured to output the control signal in accordance with the logical signal.

Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Abstract: An electronic device can execute instructions, comprising: a processing circuit; a first storage device, coupled to the processing circuit, configured to store at least one instruction and first operation data; and a second storage device, coupled to the processing circuit. The processing circuit reads at least one of the instruction and the first operation data corresponding to the read instruction from the first storage device, and the second storage device does not store the first operation data corresponding to the read instruction, the processing circuit backs up the read first operation data to the second storage device.

Abstract: Disclosed is an apparatus including a radio frequency amplifying circuit, a power supply circuit, and a bias generating circuit. The power supply circuit includes: a first power supply terminal coupled to a first ground terminal via a first capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a first switch; and a second power supply terminal coupled to a second ground terminal via a second capacitor and coupled to/decoupled from the radio frequency amplifying circuit through a second switch, wherein the first capacitor and second capacitor are coupled to/decoupled from the radio frequency amplifying circuit through the first switch and second switch respectively, the supply voltages outputted from the two power supply terminals are different, and the two switches are not concurrently turned on. The radio frequency amplifying circuit operates according to a bias voltage provided by the bias generating circuit and one of the two supply voltages.

Abstract: A receiving device comprises a first receiving circuit, for receiving a plurality of signals and comparing a plurality of signal powers of the plurality of signals with a first threshold, to generate a first plurality of comparison results; a second receiving circuit, for receiving the plurality of signals and comparing the plurality of signal powers of the plurality of signals with a second threshold, to generate a second plurality of comparison results, wherein the first threshold is smaller than the second threshold; and a control circuit, coupled to the first receiving circuit and the second receiving circuit, for determining whether an average signal power of the plurality of signals is greater than a reference power according to the first plurality of comparison results and the second plurality of comparison results, to generate a determination result.

Abstract: The present invention provides an image processing circuit, wherein the image processing circuit comprises a receiving circuit, an image dividing circuit, a first image enlargement circuit, a second image enlargement circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit receives image data, the image dividing circuit divides a pixel value of each pixel of the image data into two parts to generate first image data and second image data, the first image enlargement circuit enlarges the first image data in a linear manner to generate enlarged first image data, the second image enlargement circuit enlarges the second image data in a non-linear manner to generate enlarged second image data, and the output circuit generates an output image according to the enlarged first image data and the enlarged second image data.

Abstract: A method for scanning a keyboard circuit is provided. The keyboard circuit includes a keyboard array, output wires, input wires, and a scanning circuit. Each of the output wires is electrically coupled to a corresponding column of key units of the keyboard array, respectively. Each of the input wires is electrically coupled to a corresponding row of key units of the keyboard array, and is provided with a pull-up resistor. The method includes: turning on and connecting open-drain transistors to the ground in a scanning interval to clean charges on the output wires; turning on the open-drain transistors and connecting the open-drain transistors to the ground sequentially in a scanning duration; and receiving detected electrical levels through the input wires, and when one of the detected electrical levels is substantially equal to the electrical level of the ground, determining that the corresponding key unit is pressed.

Abstract: A phase locked device includes a digital controlled oscillator circuit, a clock signal generator circuitry, a time to digital converter circuit, and a logic control circuit. The digital controlled oscillator circuit is configured to generate a first clock signal in response to a plurality of digital codes. The clock signal generator circuitry is configured to generate a plurality of second clock signals according to the first clock signal, and to select a third clock signal and a fourth clock signal from the plurality of second clock signals according to a selection signal, in order to generate an output signal. The time to digital converter circuit is configured to detect a delay difference between the output signal and a reference signal, in order to generate the plurality of digital codes. The logic control circuit is configured to generate the selection signal according to the plurality of digital codes.

Abstract: The invention discloses a control circuit applied to a Universal Serial Bus (USB) which includes a first channel configuration pin and a second channel configuration pin. The control circuit includes: a first transistor having a first control terminal; a first resistor group coupled to the first channel configuration pin and the first transistor; a first Schottky diode having a first end and a second end, the first end being coupled to the first control terminal; a second transistor having a second control terminal; a second resistor group coupled to the second channel configuration pin and the second transistor; and a second Schottky diode having a third end and a fourth end, the third end being coupled to the second control terminal, and the fourth end being coupled to the second end of the first Schottky diode.

Abstract: An iterative decoding circuit is provided. The iterative decoding circuit includes a first concatenated decoding circuit, a second concatenated decoding circuit, and a comparator. The first concatenated decoding circuit includes a first convolutional decoder, a first deinterleaver, and a first block decoder. The second concatenated decoding circuit is coupled to the first concatenated decoding circuit, and the second concatenated decoding circuit includes a second convolutional decoder, a second deinterleaver, and a second block decoder. The comparator receives a first convolutional decoding result corresponding to a first convolutional decoding operation and a second convolutional decoding result of a second convolutional decoding operation, and is configured to compare the first convolutional decoding result with the second convolutional decoding result to generate a comparing result. The second block decoder obtains an erasure address information according to the comparing result.

Abstract: A method operates by receiving a first voltage, which is a logical signal; converting the first voltage into a second voltage using a first inverting buffer with a first pull-up resistance and a first pull-down resistance; and converting the second voltage into a third voltage using a second inverting buffer with a second pull-up resistance and a second pull-down resistance, wherein: the first pull-up resistance, the first pull-down resistance, the second pull-up resistance, the second pull-down resistance are all tunable, and a difference between the first pull-up resistance and the first pull-down resistance is approximately equal to a difference between the second pull-down resistance and the second pull-up resistance.

Abstract: The present disclosure relates to a driving circuit including a first circuit, a transistor switch, and a voltage level conversion circuit. The first circuit includes an operational amplifier and a feedback circuit, and is configured to output a first signal (e.g., an analog signal). The feedback circuit is configured to feed back the first signal to the operational amplifier. A source terminal and a drain terminal of the transistor switch are respectively electrically coupled to the operational amplifier and an output pin of the driving circuit. The voltage level conversion circuit is connected to the source terminal and a gate terminal of the transistor switch. When the voltage level conversion circuit is enabled, a voltage difference between the gate terminal and the source terminal of the transistor switch is controlled to a set value, so that the first signal is output to the output pin through the transistor switch.

Abstract: A device having a substrate, a dielectric slab attached upon the substrate, a coil including a plurality of metal segments laid out on a first metal layer secured by the dielectric slab, the coil being substantially laterally symmetrical with respect to a central line from a top view perspective, and a shield laid out on a second metal layer secured by the dielectric slab and configured in a tree topology. The shield is substantially laterally symmetrical with respect to the central line from the top view perspective, the tree topology including a plurality of clusters of branches, wherein each of said plurality of clusters of branches is associated with a respective metal segment of the coil and includes a primary branch and at least one set of secondary branches that are branched from the primary branch, parallel to one another, and oriented at a substantially forty-five-degree angle with respect to the respective metal segment from the top view perspective.

Abstract: The present invention provides a voltage difference measurement circuit comprising a level shifting circuit, an ADC and a calculation circuit. In the operations of the voltage difference measurement circuit, the level shifting circuit adjusts levels of a supply voltage and a ground voltage to generate an adjusted supply voltage and an adjusted ground voltage, respectively. The ADC performs an analog-to-digital converting operation upon the adjusted supply voltage and the adjusted ground voltage to generate a first digital value and a second digital value, respectively. The calculation circuit calculates a voltage difference between the supply voltage and the ground voltage according to the first digital value and the second digital value.

Abstract: An object tracking method includes the following operations: detecting a first area of an object in a first video frame based on a deep learning model, in order to forecast a forecast area of the object in a forecast video frame according to the first video frame and the first area; detecting a second area of the object in a second video frame based on the deep learning model; and determining a correlation between the forecast area and the second area, in order to track the object.

Abstract: The present invention provides a wireless earphone, wherein the wireless earphone includes a first pin, a microprocessor and a power management unit, the first pin is arranged to connect to an external charging device, the microprocessor includes a core circuit and a wakeup circuit coupled to the first pin, and the power management unit includes an uninterruptible power area for providing a power to the wakeup circuit. In the operations of the wireless earphone, when the core circuit is at a sleep mode, if the wakeup circuit detects that a voltage level of the first pin changes, the wakeup circuit generates a wakeup signal to wake up the core circuit.

Abstract: A multi-member Bluetooth device for communicating data with a source Bluetooth device acting as a master in a first piconet. The multi-member Bluetooth device includes a main Bluetooth circuit acting as a slave in the first piconet and as a master in a second piconet, and an auxiliary Bluetooth circuit acting as a slave in the second piconet. The main Bluetooth circuit generates a first slave clock and a second main clock according to a first main clock generated by the source Bluetooth device, with which both the first slave clock and the second main clock are synchronized. The auxiliary Bluetooth circuit generates a second slave clock and a third slave clock according to the second main clock, with which both the second slave clock and the third slave clock are synchronized. The auxiliary Bluetooth circuit sniffs Bluetooth packets transmitted through the first piconet from the source Bluetooth device.

Abstract: An auxiliary Bluetooth circuit of a multi-member Bluetooth device for communicating data with a source Bluetooth device acting as a master in a first piconet. A main Bluetooth circuit of the multi-member Bluetooth device acts as a slave in the first piconet, acts as a master in a second piconet, and generates a first slave clock and a second main clock according to a first main clock generated by the source Bluetooth device, with which both the first slave clock and the second main clock are synchronized. The auxiliary Bluetooth circuit acts as a slave in the second piconet and generates a second slave clock and a third slave clock according to the second main clock, with which both the second slave clock and the third slave clock are synchronized. The auxiliary Bluetooth circuit sniffs Bluetooth packets transmitted through the first piconet from the source Bluetooth device.

Abstract: A main Bluetooth circuit and an auxiliary Bluetooth circuit of a multi-member Bluetooth device are disclosed. The multi-member Bluetooth device is utilized for communicating data with a source Bluetooth device, and the source Bluetooth device acts as a master in a first piconet. The main Bluetooth circuit acts as a slave in the first piconet, and acts as a master in a second piconet. The auxiliary Bluetooth circuit acts as a slave in the second piconet. The main Bluetooth circuit generates a first slave clock and a second main clock synchronized with a first main clock generated by the source Bluetooth device, and samples a first audio data to be playback. The auxiliary Bluetooth circuit generates a second slave clock and a third slave clock synchronized with the second main clock, and samples a second audio data to be playback.