Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.

Abstract: A clock generator and method operate by receiving an input clock; cascading a first inverter, a second inverter, a third inverter, and a fourth inverter in a ring topology to output a first phase, a second phase, a third phase, and a fourth phase of an interim clock; enabling the second inverter and the fourth inverter during a first phase of the input clock and enforcing a complementary relation between the second phase and the fourth phase of the interim clock by using a fifth inverter and a sixth inverter configured in a cross-coupling topology; enabling the first inverter and the third inverter during a second phase of the input clock and enforcing a complementary relation between the first phase and the third phase of the interim clock by using a seventh inverter and an eighth inverter configured in a cross-coupling topology.

Abstract: Disclosed is a voltage regulator. The voltage regulator includes a reference voltage circuit, a noise cancellation circuit, an error amplifier, a pass transistor and a voltage divider. The voltage regulator can cancel the noise generated by the reference voltage circuit and the error amplifier, and also can improve its Power Supply Rejection Ratio (PSRR).

Abstract: Provided herein are a headphone amplifier circuit for a headphone driver, an operation method thereof, and a universal serial bus (USB) interfaced headphone device using the same. The output stage of the headphone amplifier circuit is improved to have a differential output structure so as to effectively solve the crosstalk issue and increase the isolation between the left and the right channels such that the audio content presents a spatial perception and a distance perception more specifically.

Abstract: Provided is a fast divider including an initial parameter setting unit and an arithmetic unit. The arithmetic unit is coupled to the initial parameter setting unit that receives a divisor and a dividend, and sets a plurality of initial parameters of a sequence according to the divisor and the dividend. The plurality of initial parameters includes an initial term, a first term and a common ratio having an absolute value smaller than 1. The arithmetic unit stores a recurrence relation of the sequence and iteratively computes a quotient using the recurrence relation according to the plurality of initial parameters. The recurrence relation indicates that a (k+1)th term is equal to a product of a kth term multiplied by a sum of the common ratio and 1 subtracted by a product of a (k?1)th term multiplied by the common ratio. k is an integer larger than or equal to 1.

Abstract: A USB control circuit of a USB hub device includes: an upstream MAC-layer circuit; a downstream MAC-layer circuit; a first USB PHY-layer circuit; a second USB PHY-layer circuit; a first switch circuit for communicating data with an upstream port through the first USB PHY-layer circuit; a second switch circuit for communicating data with a downstream port through the second USB PHY-layer circuit; a control signal transmission interface; a signal repeater circuit; and a control unit configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples the upstream MAC-layer circuit or the signal repeater circuit with the first USB PHY-layer circuit, while the second switch circuit selectively couples the downstream MAC-layer circuit or the signal repeater circuit with the second USB PHY-layer circuit.

Abstract: An auxiliary channel transceiving circuit includes: a first node and a second node; a first voltage-dividing circuit for generating a first received signal according to a signal from the first node; a second voltage-dividing circuit for generating a second received signal according to a signal from the second node; a first receiver amplifying circuit for amplifying the first received signal to generate a first amplified signal; a second receiver amplifying circuit for amplifying the second received signal to generate a second amplified signal; a comparison circuit for comparing the first amplified signal with the second amplified signal to generate a received signal; a first transmitter amplifying circuit for generating a first output signal according to a transmitting signal; and a second transmitter amplifying circuit for generating a second output signal according to the transmitting signal. The auxiliary channel transceiving circuit is not required to cooperate with traditional capacitors.

Abstract: A data recovery circuit includes: a first comparison circuit for comparing two analog data signals to output a first and a second comparison signals having opposite logic values when a positive clock signal stays at an active level, and for configuring the first and second comparison signals to have a same logic value when the positive clock signal stays at an inactive level; a second comparison circuit for comparing the two analog data signals to output a third and a fourth comparison signals having opposite logic values when a negative clock signal stays at the active level, and for configuring the third and fourth comparison signals to have the same logic value when the negative clock signal stays at the inactive level; and a data signal generating circuit for generating a digital data signal according to the first through fourth comparison signals.

Abstract: A patterned shield structure applied to an integrated circuit (IC) is disposed between an inductor and a substrate of the integrated circuit. The patterned shield structure includes a center structure unit, a first patterned structure unit, and a second patterned structure unit. The center structure unit includes a first sub-center structure unit and a second sub-center structure unit. The second sub-center structure unit and the first sub-center structure unit are symmetrically disposed with respect to a middle of the center structure unit. The first patterned structure unit is disposed on one side of the center structure unit. The second patterned structure unit is disposed on another side of the center structure unit. The second patterned structure unit and the first patterned structure unit are symmetrically disposed with respect to the center structure unit.

Abstract: A transceiving circuit, which comprises: a transmitting circuit, configured to transmit a test signal; a receiving circuit, comprising a mixer configured to receive a plurality of predetermined DC bias voltage groups, wherein the receiving circuit generates a plurality of output signals according to the test signal while the mixer operates at the predetermined DC bias voltage groups; a frequency domain analyzing circuit, configured to transform the output signals to a plurality of frequency domain signals; and a DC bias voltage generating circuit, configured to generate a function according to the frequency domain signals and the predetermined bias voltage groups, and configured to generate a first DC bias voltage group to the mixer according to the function.

Abstract: A control method and a control system for an audio device are disclosed. The control method and control system are applied to a USB audio adapter that includes an analog audio interface and is connected to a host. The control method includes steps of: detecting whether the analog audio interface is connected to a target device or detecting a function of the target device, and generating a detection result accordingly; controlling the USB audio adapter to operate in a disconnected mode; and controlling the USB audio adapter to continue operating in the disconnected mode according to the detection result, or controlling, according to the detection result, the USB audio adapter to operate in a connected mode and transmit audio data to the host and/or receive audio data from the host.

Abstract: An apparatus includes a first AC (alternating current) coupling circuit configured to receive a first end of a differential signal and output a first coupled signal in accordance with a bias voltage; a second AC coupling circuit configured to receive a second end of the differential signal and output a second coupled signal in accordance with the bias voltage; a first complementary joint-control cascode pair configured to shunt the first end of the differential signal to a DC (direct current) node in accordance with a joint control by the first coupled signal and the second coupled signal; and a second complementary joint-control cascode pair configured to shunt the second end of the differential signal to the DC node in accordance with a joint control by the first coupled signal and the second coupled signal. A related method is also provided.

Abstract: An infrared (IR) learning device is disclosed. A hardware device of the IR learning device amplifies, shapes, and samples an IR signal to acquire a better digital signal related to the IR signal. A software device of the IR learning device calculates the waveform of the IR signal and the frequency of a carrier wave of the IR signal according to the digital signal related to the IR signal. Accordingly, the IR learning device can learn the IR signal emitted from an external device by the hardware device and the software device.

Abstract: An inductor device includes a conductor and a connector. The conductor includes a first ring-type structure and a second ring-type structure. The second ring-type structure is coupled to the first ring-type structure. The connector is coupled to the first ring-type structure and the second ring-type structure, and is configured to selectively connect the first ring-type structure and the second ring-type structure such that the conductor forms single loop.

Abstract: The present disclosure provides a receiving apparatus for preprocessing at least one segment data packet to a data packet. The receiving apparatus includes a packet parser, a data memory, a decrypt engine, a transmission engine, a header processing unit and a controller. The packet parser fetches segment-packet-header information from a segment packet header of each segment data packet. The decrypt engine decrypts an encrypted data of each segment data packet to obtain a segment payload and a QUIC private header including sequence information. The transmission engine transmits the segment payload to a specific location of a system memory. The header processing unit calculates packet information and updates the segment packet header stored in the data memory to generate a packet header. The controller controls the transmission engine based on the sequence information to output the packet header to the system memory for generating the data packet.

Abstract: A network device includes a packet classifying unit and a packet processing unit. The packet processing unit includes processors coupled in series. Each processor includes a storage unit and an operating unit. Data packets are classified into packet types corresponding to different pipelines by the packet classifying unit. The storage unit stores characteristic values and operation data corresponding to different pipelines. The operating unit processes data packets output from the previous stage (e.g., classified data packets) in accordance with their packet types, characteristic values and the corresponding operation data.

Abstract: An integrated inductor structure includes a guard ring, a patterned ground shield, and an inductor. The guard ring includes an inner ring, an outer ring, and an interlaced structure. The inner ring is disposed in a first metal layer, and includes at least two inner ring openings. The outer ring is disposed in a second metal layer, and includes at least one outer ring opening. The interlaced structure is coupled to one of the at least two inner ring openings and the outer ring opening in an interlaced manner, such that the outer ring opening is enclosed. The patterned ground shield is disposed at an inner side of the inner ring, and coupled to the inner ring and the outer ring. The inductor is formed above the guard ring and the patterned ground shield.

Abstract: An audio processing device that includes a first ADC, a second ADC, a register and a processing circuit is provided. The processing circuit executes a first audio application program corresponding to a first analog input audio stream and assigns the first analog input audio stream to the first ADC. When the processing circuit identifies that a second audio application program also corresponds to the first analog input audio stream, the processing circuit control the first ADC to process the first analog input audio stream. When second audio application program corresponds to a second analog input audio stream, the processing circuit assigns the second analog input audio stream to the second ADC for processing such that the first and the second ADCs process the first and the second analog input audio stream respectively.

Abstract: The present invention discloses a wireless communication method carried out by a wireless transmitter capable of offering an unintended wireless device a chance of starting or proceeding with a transmission procedure during a transmission duration of the wireless transmitter. An embodiment of said wireless communication method comprises the following steps: preparing a packet carrying an indication of a clear channel assessment (CCA) threshold level for an unintended wireless device to decide whether to execute a transmission procedure; and transmitting the packet to an intended wireless device under a protocol by which the unintended wireless device is expected to abide.

Abstract: A successive approximation register analog-to-digital converter capable of accelerating reset comprises: a sampling circuit generating at least one output signal(s) according to at least one input signal(s); a comparator generating at least one comparator output signal(s) according to the at least one output signal(s) and a reset signal; a control circuit controlling the operation of the sampling circuit according to the at least one comparator output signal(s) or the equivalent thereof, and generating the reset signal; a first reset wire circuit outputting the reset signal to the comparator so that a first circuit of the comparator is reset when the value of the reset signal is a first value; and a second reset wire circuit outputting the reset signal to the comparator so that a second circuit of the comparator is synchronously reset when the value of the reset signal is the first value.