Abstract: An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.

Abstract: The invention relates to a system for interference cancellation and method thereof. The system includes a receiver, a transmitter, and a channel estimating and equalizing device. The transmitter and the receiver use different wireless communication technologies to transmit and receive data. The channel estimating and equalizing device can estimate the channel between the transmitter and the receiver for interference cancellation. The embodiments of the invention provide a system and a method thereof for reducing interferences generated when using one wireless communication technology to transmit signals but using another wireless communication technology to receive signals by using digital baseband signals.

Abstract: An integrated circuit installed in an electronic device having an external connector, including: a monitor circuit and a control circuit. The monitor circuit coupled to the external connector is configured to monitor a code generated from a user's input and inputted via the external connector, the monitor circuit generating a control signal according to the code; and the control circuit coupled to the monitor circuit and at least a circuit block of the electronic device is configured to control the external connector to be coupled to the circuit block according to the control signal; wherein a testing operation is executed in response to a testing signal inputted to the control circuit via the external connector for checking and modifying a status of the circuit block of the electronic device after the external connector is coupled to the control circuit.

Abstract: A circuit including a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, a second PMOS transistor, and a second NMOS transistor. A source, a gate, and a drain of the first PMOS transistor connect to a first node, a second node, and a third node, respectively. A source, a gate, and a drain of the first NMOS transistor connect to a fourth node, the third node, and the second node, respectively. A source, a gate, and a drain of the second PMOS transistor connect to the third node, the fourth node, and the second node, respectively. Finally, a source, a gate, and a drain of the second NMOS transistor connect to the second node, the first node, and the third node, respectively.

Abstract: A DC offset calibration circuit for calibrating DC offset with multi-level method includes analog DC offset cancellation unit and digital DC offset cancellation unit, wherein analog DC offset cancellation unit includes first amplifier and integrator, first amplifier receives analog signal with DC offset, and transmits to integrator, and integrator transmits first feedback signal to first amplifier to output amplified signal with fixed DC offset, and digital DC offset cancellation unit includes comparator, digital circuit, digital-to-analog converter and second amplifier, where second amplifier receives amplified signal with fixed DC offset and transmits to comparator for determining DC offset value and transmitting to digital circuit, digital circuit generates logical result according to DC offset value and transmits to digital-to-analog converter, and therefore digital-to-analog converter accordingly generates second feedback signal to second amplifier, to calibrate DC offset value on second amplifier.

Abstract: An apparatus comprises: a main frequency quadrupler configured to receive a first clock and output a second clock of a quadruple frequency in accordance with a first control signal and a second control signal, wherein a timing difference between a first rising edge and a second rising edge of the second clock is controlled by the second control signal, and a timing difference between the first rising edge and a third rising edge of the second clock is controlled by the first control signal; an auxiliary frequency quadrupler configured to receive the first clock and output a third clock of the quadruple frequency with a timing offset controlled a third control signal; and a calibration circuit configured to generate and output the first control signal, the second control signal, and the third control signal in accordance with a timing difference between the second clock and the third clock.

Abstract: An image contrast enhancement method and an apparatus thereof are disclosed, which calculate the degree of influencing the clarity according to the influence feature (e.g., heavy fog, dust, smoke, or etc.) in the image, and then adjust the brightness of the pixels corresponding to features of influencing the clarity according to the degree, thereby enhancing image contrast and removing phenomenon of influencing the clarity in the image.

Abstract: A method comprises: receiving a differential input signal; converting the differential input signal into a first transmitted current and a second transmitted current using a common-source differential pair biased by a bias current; launching the first transmitted current and the second transmitted current onto a first port of a differential transmission line; receiving a first received current and a second received current from a second port of the differential transmission line; buffering the first received current and the second received current into a first output current and a second output current, respectively, using a current buffer, wherein the current buffer comprises: a common-gate amplifier pair, a first cross-coupling network configured to provide a negative feedback on the input side of the current buffer to reduce an input impedance of the current buffer, and a second cross-coupling network configured to provide a positive feedback on the output side of the current buffer to boost an output impe

Abstract: A data backup method for backing up target data, through a driver module, from a first storage device to a second storage device is disclosed. The first storage device includes a first storage unit that stores the target data, and a first control unit that accesses the first storage unit based on a first logical-to-physical mapping table. The second storage device includes a second storage unit and a second control unit that accesses the second storage unit based on a second logical-to-physical mapping table. The method includes steps of: reading the target data from the first storage unit without accessing the first logical-to-physical mapping table and transmitting the target data to the driver module; transmitting the target data to the second control unit; and writing the target data to the second storage unit without accessing the second logical-to-physical mapping table.

Abstract: A method of driving a network device for outputting signals to a physical network transmission medium. The network device includes a DAC circuit that comprises a plurality of digital-to-analog conversion units. Each digital-to-analog conversion unit includes a first auxiliary current source and a second auxiliary current source. The method includes the steps of: detecting a length of the physical network transmission medium; generating a control signal according to the length; generating a bias signal according to the control signal; applying the bias signal to the first auxiliary current source and the second auxiliary current source to control the currents of the first auxiliary current source and the second auxiliary current source.

Abstract: A control method includes detecting an operational command to a first memory unit, interrupting an operational status of a second memory unit, asserting the operational command corresponding to the first memory unit, and recovering the operational status of the second memory unit. The first memory unit and the second memory unit correspond to the same channel.

Abstract: A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.

Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.

Abstract: An impedance calibration device provided includes a timing device, a first transmitter, a first variable resistor, a second variable resistor and a first receiver. The first variable resistor is used to receive a first adjustment code. The second variable resistor is used to receive a second adjustment code. The first receiver generates a first contact digital signal according to a first contact voltage. The first receiver generates a first terminate digital signal according to a first terminate voltage and the first adjustment code. The first receiver generates a first load digital signal according to a load voltage and the second adjustment. The timing device dynamically adjust the first adjustment code and the second adjustment code according to the first contact digital signal, the first terminate digital signal and the first load digital signal.

Abstract: An apparatus is configured to receive a two-phase input clock and output a four-phase output clock, the apparatus includes a first data latch and a second data latch configured in a ring topology with a negative feedback based on inter-connection through a four-phase level-shifted clock, the first data latch configured to receive a fourth phase and a second phase of the level-shifted clock and output a first phase and a third phase of the output clock along with a first phase and a third phase of the level-shifted clock in accordance with a first phase of the input clock, the second data latch configured to receive the first phase and the third phase of the level-shifted clock and output a second phase and a fourth phase of the output clock along with the second phase and the fourth phase of the level-shifted clock in accordance with a second phase of the input clock.

Abstract: A method of interference cancellation includes the following steps: performing a take-energy operation on a to-be-sent signal at multiple times to generate multiple to-be-sent signal powers; performing a first high-pass operation on the to-be-sent signal powers to generate a to-be-sent high-pass result; performing a second high-pass operation on a received signal to generate a received high-pass result; adjusting multiple filter coefficients according to the to-be-sent high-pass result and the received high-pass result; and generating a recover signal according to the filter coefficients.

Abstract: A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current.

Abstract: A combo-plug detecting circuit for use in an audio CODEC is provided. The combo-plug detecting circuit is used to determine the contact configuration of the audio plug, to ensure that the audio plug belonging to the differential structure can be compatible with the audio CODEC.

Abstract: A double data rate synchronous dynamic random access memory includes a control circuit and an output driving circuit. The control circuit provides a first voltage, a second voltage, a third voltage and a fourth voltage. The output driving circuit couples to the control circuit and includes a pull-up circuit, a pad and a pull-down circuit. When a voltage of the pad rises from the fourth voltage to the first voltage, a voltage between a drain and a source of a second driving transistor in the pull-down circuit is between the third voltage and the fourth voltage. When a voltage of the pad falls from the first voltage to the fourth voltage, a voltage between a drain and a source of a first driving transistor in the pull-up circuit is between the first voltage and the second voltage.