Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.

Abstract: An image-filtering device for filtering an image that includes a pixel difference computing module, an adaptive brightness adjusting module, a weighting computing module and a filter computing module is provided. The pixel difference computing module uses any one of the pixels as a central pixel within a pixel window to compute pixel absolute differences between the central pixel and every pixels within the pixel window. The adaptive brightness adjusting module multiplies each of the pixel absolute differences with an adjusting parameter to generate adjusted pixel absolute differences. The weighting computing module generates weighting values according to the adjusted pixel absolute differences. The filter computing module performs convolution according to the pixel value of each of the pixels within the pixel window and the corresponding weighting values to generate a filtering result of the central pixel.

Abstract: A control circuit of a master-side game console includes: a processor and a storage circuit for storing a computer program product.

Abstract: A control circuit of a client-side game console includes: a processor and a storage circuit for storing a computer program product. The processor is arranged to operably execute the computer program product to perform following operations: establishing networking connection between the client-side game console and a master-side game console; receiving client-side input values generated by a user control device of the client-side game console; transmitting the client-side input values to the master-side game console; receiving a target instruction and a pseudo clock indicator value transmitted from the mater-side game console; executing the target instruction in a client-side emulating environment based on the pseudo clock indicator value; and rendering an updated client-side game screen according to execution results of the target instruction and displaying the updated client-side game screen on a display device.

Abstract: An electrostatic discharge protection element is provided, which leads out the electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge. The electrostatic discharge protection element includes an I/O pad, conductor, and a gap structure. The I/O pad is connected between the I/O terminal and the internal circuit, and the conductor is connected to a ground terminal. The gap structure is disposed between the I/O pad and the conductor, which is configured to establish a path from the I/O pad to the conductor connected to the ground terminal for conducting the electrostatic discharge current.

Abstract: The present invention discloses a differential signal skew detecting circuit configured to detect a skew of a differential signal. An embodiment of the circuit includes: a common mode voltage outputting circuit configured to output a common mode reference voltage and a common mode skew voltage; and a skew detecting circuit configured to inspect the common mode reference voltage and the common mode skew voltage according to a clock signal so as to output a skew detection value, in which when the skew detecting circuit detects the skew of the differential signal, the skew detection value is a first value, and when the skew detecting circuit detects no skew of the differential signal, the skew detection value is a second value.

Abstract: A control method, which is adapted to a phase interpolator configured to generate an output signal based on a current distribution ratio, includes following operations: selecting a first input pair and a second input pair from the phase interpolator; sequentially switching currents associated with the current distribution ratio from the first input pair to flowing through the second input pair, in order to adjust a phase of the output signal to correspond to a first phase interval; and after all of the currents flow through to the second input pair, selecting the second input pair and a third input pair from the phase interpolator, and adjusting the current distribution ratio to correspond the phase of the output signal to a second phase interval, in which the first phase interval and the second phase interval are continuous.

Abstract: An electronic device includes a first planar inductor and a second planar inductor. The first planar inductor includes at least a first ring structure and a second ring structure interconnected electrically for generating a first magnetic field having a first direction and a second magnetic field having a second direction respectively, wherein the first direction is different from the second direction. The second planar inductor includes at least a third ring structure and a fourth ring structure interconnected electrically for generating a third magnetic field having a third direction and a fourth magnetic field having a fourth direction respectively, wherein the third direction is different from the fourth direction. The first ring structure at least partially overlaps the third ring structure to form a first overlap region, and the second ring structure at least partially overlaps the fourth ring structure to form a second overlap region.

Abstract: A noise cancellation device includes an anti-noise filter circuit, an output circuit, and a detection circuit. The anti-noise filter circuit provides a corresponding one of transfer functions to process a digital signal, in order to generate a noise cancellation signal, in which the transfer functions are different from each other. The output circuit mixes the noise cancellation signal, a reference signal, and an input signal to generate a mixed signal, and generates a sound output signal based on the mixed signal, in which the digital signal is associated with the sound output signal. The detection circuit controls the anti-noise filter circuit to provide the corresponding one of the transfer functions according to a comparison result of a first ratio and a first threshold value, in which the first ratio is a ratio of a first power of the mixed signal to a second power of the digital signal.

Abstract: This invention discloses a memory control circuit and a method thereof. The memory control method includes the steps of: transmitting a first clock to a serial peripheral interface (SPI) NOR flash memory; transmitting a read instruction to the SPI NOR flash memory; waiting for a read waiting time period, which is associated with a specification of the SPI NOR flash memory and a cycle of the first clock; waiting for a delay time period, which is associated with a delay setting value and a cycle of a second clock different from the first clock; receiving read data returned from the SPI NOR flash memory; and adjusting the delay time period according to whether the read data are correct or not. This invention improves the stability of read operation of the SPI NOR flash memory and has advantages of simple circuit and flexible adjustment.

Abstract: An envelope-tracking power supply modulator (ETSM) supplies power to a radio frequency power amplifier (RFPA) of a radio frequency (RF) circuit according to a baseband envelope signal. The ETSM includes a linear amplifier, a capacitor, a single inductor multiple output (SIMO) switch-mode converter, and a controller. The linear amplifier receives the baseband envelope signal, and has its output terminal coupled to a power input of the RFPA. One terminal of the capacitor is coupled to a reference voltage, and the other terminal is coupled to a power input of the linear amplifier. The SIMO switch-mode converter includes two output terminals. One of the output terminals is coupled to the capacitor and the power input of the linear amplifier, and the other of the output terminals is coupled to the output terminal of the linear amplifier and the power input of the RFPA. The controller controls the SUMO switch-mode converter.

Abstract: A receiving device comprises a signal detection unit, a reliability unit coupled to the signal detection unit and a decoding unit coupled to the signal detection unit and the reliability unit. The signal detection unit is for receiving a plurality of compensated symbols on a plurality of subcarriers, to generate a plurality of soft information and a plurality demodulated symbols of the plurality of compensated symbols according to the plurality of compensated symbols. The reliability unit is for generating a plurality of weights of the plurality of soft information according to a plurality of reliability information of the plurality of subcarriers. The decoding unit is for decoding the plurality of demodulated symbols according to the plurality of soft information and the plurality of weights, to generate a plurality of decoded bits.

Abstract: Disclosed is a correcting device of successive approximation analog-to-digital conversion. The correcting device includes a successive approximation register analog-to-digital converter (SAR ADC) and a digital circuit. The SAR ADC is configured to generate a digital output. The digital circuit is configured to determine whether the digital output conforms to a metastable output, and correct the digital output when the digital output conforms to the metastable output. The metastable output is related with a metastable binary comparison-results sequence including successive K comparison results such as 110000 or 001111. The K comparison results include a first comparison result, a second comparison result and successive M comparison results in turn. The first comparison result and the second comparison result are the same; the M comparison results are the same; each of the first comparison result and the second comparison result is different from any of the M comparison results.

Abstract: An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough.

Abstract: A sigma delta modulator includes an integrator, a quantizer, a randomization circuit, and a digital to analog converter circuit. The integrator is configured to integrate an analog signal, in order to generate a first signal, in which the analog signal is a sum of an input signal and a second signal. The quantizer is coupled to the integrator and configured to quantize the first signal to generate a digital signal which has a plurality of bits. The randomization circuit is coupled to the quantizer, and is configured to randomize partial bits in the plurality of bits of the digital signal, in order to generate first control signals. The digital to analog converter (DAC) circuit is coupled to the quantizer and the randomization circuit, and is configured to generate the second signal according to the first control signals and remaining bits in the plurality of bits of the digital signal.

Abstract: An frequency down-converter includes a mixer configured to receive a RF (radio frequency) signal having a first end and a second end and output an intermediate signal comprising a first end and a second end in accordance with a LO (local oscillator) signal having a first end and a second end, wherein the first end and the second end of the LO signal jointly form a two-phase periodic signal of a fundamental frequency approximately equal to a mean frequency of a desired component of the RF signal.

Abstract: An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.

Abstract: An integrated inductor structure includes a first spiral coil, a second spiral coil and a connection metal segment. The first spiral coil includes a plurality of metal segments, a bridging segment and first to fourth terminals. The bridging segment connects the metal segments. The second spiral coil has fifth and sixth terminals. The connecting metal segment connects the third and fifth terminals and the fourth and the sixth terminals. The integrated inductor structure uses the first and second terminals as its input and output terminals. The first and third terminals are on a first imaginary line, which passes a central region of a region surrounded by the first spiral coil. The bridging segment and the central region of the region are on a second imaginary line. An included angle between the two imaginary lines is equal to or greater than 45 degrees and equal to or smaller than 90 degrees.

Abstract: A Universal Serial Bus (USB) converter circuit includes: a High Definition Multimedia Interface (HDMI) transceiver circuit, a signal converting circuit and a USB receptacle, wherein the HDMI transceiver circuit arranged to transmit/receive a HDMI signal, wherein the HDMI transceiver circuit includes at least a video signal and a plurality of processing signals; the signal converting circuit coupled to the HDMI transceiver circuit is arranged to execute a converting operation to processing a conversion between the plurality of processing signals and A USB signal; and the USB receptacle coupled to the signal converting circuit includes a USB signal pin and a set of video signal pin, wherein the USB signal is transmitted/received with an electronic device through the USB pin, and the video signal is transmitted/received with the electronic device through the set of video signal pin.

Abstract: The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.