Abstract: A calibration circuit and calibration method for a successive approximation register analog-to-digital converter (SAR ADC) are disclosed. The SAR ADC includes a comparator and generates a digital code. The calibration method includes the following steps: (a) creating a voltage difference between two inputs of the comparator, with the absolute value of the voltage difference being smaller than or equal to the absolute value of the voltage corresponding to the least significant bit (LSB) of the digital code; (b) updating a count value according to whether a timer of the SAR ADC issues a time-out signal, the timer issuing the time-out signal after a delay time has elapsed; (c) repeating steps (a) through (b) a predetermined number of times; (d) calculating a probability based on the predetermined number of times and the count value; and (e) adjusting the delay time according to the probability.

Abstract: A combo chip is provided. The combo chip is applicable to an USB connector, and includes an USB type-C circuit, an USB non-type-C circuit, a switch unit, and a mode control unit. The switch unit is connected to the USB type-C circuit and the USB non-type-C circuit, and the mode control unit is connected to a control terminal of the switch unit. After performing one or more mode determination procedures, the mode control unit controls the switch unit to connect the USB type-C circuit to a first pin and a second pin while disconnecting the USB non-type-C circuit from the first pin and the second pin, or otherwise controls the switch unit to connect the USB non-type-C circuit to the first pin and the second pin while disconnecting the USB type-C circuit from the first pin and the second pin.

Abstract: An operational amplifier includes: a first gain stage for generating a second signal based on a first signal transmitted from a prior stage circuit; a second gain stage for generating an output signal based on the second signal; multiple candidate capacitors; and a capacitor selection circuit for switching the coupling relationship of the multiple candidate capacitors based on the magnitude of an input signal of the prior stage circuit, so that only a portion of the multiple candidate capacitors could be coupled to the second gain stage at a time.

Abstract: A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

Abstract: A sample-and-hold amplifier includes: a switched capacitor network for conducting a sample -and-hold operation on an input signal to generate a first signal; and an operational amplifier coupled with the switched capacitor network and including multiple candidate capacitors; wherein the operational amplifier is arranged to operably generate an output signal based on the first signal, and to operably switch coupling relationship of the multiple candidate capacitors based on the magnitude of the input signal, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

Abstract: A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.

Abstract: The present disclosure includes an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a search value according to a communication index and a modulation type or determine the search value according to a predetermined value, in which the communication index is related to a reception signal or a derivative thereof, the search value is associated with a search range, and a number of candidate signal value(s) in the search range is not greater than a number of all candidate signal values of the modulation type. The ML detecting circuit is configured to execute an ML calculation according to the search value and one of the reception signal and the derivative thereof, so as to calculate a log likelihood ratio of every candidate signal value in the search range.

Abstract: An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

Abstract: The instant disclosure provides an integrated circuit device including a transmission line which includes a first ground line and a signal line. The first ground line includes a first pad, a second pad and a first bonding wire that is a bond wire structure connecting the first pad and the second pad. The first signal line includes a third pad, a fourth pad and a second bonding wire that is a bond wire structure connecting the third pad and the fourth pad.

Abstract: A wireless communication system under a contention-based protocol comprises an access point and at least one station, wherein the station is arranged for wirelessly communicating with the access point under the contention-based protocol. In the operations of the wireless communication system, the access point broadcasts a polling usage sequence to assign a time slot for the station, and the station subsequently uses the assigned time slot to transmit a data packet to the access point.

Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.

Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.

Abstract: A control circuit of a client-side game console includes: a processor and a storage circuit for storing a computer program product. The processor is arranged to operably execute the computer program product to perform following operations: establishing networking connection between the client-side game console and a master-side game console; receiving client-side input values generated by a user control device of the client-side game console; transmitting the client-side input values to the master-side game console; receiving a target instruction and a pseudo clock indicator value transmitted from the mater-side game console; executing the target instruction in a client-side emulating environment based on the pseudo clock indicator value; and rendering an updated client-side game screen according to execution results of the target instruction and displaying the updated client-side game screen on a display device.

Abstract: A control circuit of a master-side game console includes: a processor and a storage circuit for storing a computer program product.

Abstract: The present disclosure provides a weighting-type data relocation control device for controlling data relocation of a non-volatile memory which includes used blocks and unused blocks. Each used block is associated with a first parameter and a second parameter. The control device executes the following steps: multiplying the first and second parameters by a first and a second weightings respectively to obtain a priority index, in which at least one of the parameters and/or at least one of the weightings relate(s) to a thermal detection result; comparing the priority index with at least a threshold to obtain a comparison result; and if the comparison result corresponding to a used storage block of the used blocks reaches a predetermined threshold, transferring valid data of the used storage block to one of the unused blocks.

Abstract: An electronic apparatus and heat dissipation and EMI shielding structure thereof are provided. The electronic apparatus includes a substrate, at least one chip disposed on the substrate, and the heat dissipation and EMI shielding structure. The heat dissipation and EMI shielding structure covers the chip and includes a shielding frame and a heat dissipation element. The shielding frame has an opening to expose the chip, and the heat dissipation element is disposed on the shielding frame and covers the opening. The conjunction of the shielding frame and the heat dissipation element can protect the chip from being interfered with electromagnetic waves, and the heat generated by the chip can be dissipated by the heat dissipation element.

Abstract: A method of receiving an RF signal is applied to a receiving circuit of a wireless communication system and amplifies the RF signals according to an analog gain. The RF signal includes data signals and interference signals. The method includes steps of: employing a low noise amplifier (LNA) to amplify the RF signal according to a first gain to generate an amplified RF signal, the first gain being associated with a first bias signal; detecting the amplified RF signal in an RF band to generate a control signal corresponding to the power of the amplified RF signal, the control signal being an analog signal; providing the first bias signal to the LNA according to the control signal; down-converting the amplified RF signal to generate an intermediate frequency or baseband signal; and filtering the intermediate frequency or baseband signal to filter out the interference signal and thus obtain the data signal.

Abstract: A circuit having a first Gilbert cell mixer of a first type configured to receive phases of first and second signals and output a first current pair to a first node and a second node; a first Gilbert cell mixer of a second type configured to receive output a second current pair to the first node and the second node; a second Gilbert cell mixer of the first type configured to receive phases of the first and second signals and output a third current pair to the first node and the second node; a second Gilbert cell mixer of the second type configured to output a fourth current pair to the first node and the second node; a cross-coupling inverter pair configured to cross couple the first node and the second node; and a load placed across the first node and the second node and configured to resonate at a frequency approximately equal to either a sum of a frequency of the first signal and a frequency of the second signal or a difference of the frequency of the first signal and the frequency of the second signal.

Abstract: A dual-mode signal transceiver includes a first transmitter circuit, a second transmitter circuit, and a receiver circuit. The first transmitter circuit is configured to operate in a first mode and configured to process a first input signal according to a first oscillating signal, in order to output a first output signal. The second transmitter circuit is configured to operate in a second mode and configured to process a second input signal according to a second oscillating signal, in order to output a second output signal, wherein a frequency of the second oscillating signal is not an integral multiple of a frequency of the first oscillating signal. The receiver circuit is configured to process an external signal associated with one of the first mode and the second mode according to the first oscillating signal, in order to read data associated with the external signal.

Abstract: A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.