Abstract: A current sense circuit is provided. The circuit includes a current mirror circuit QN1, QN2, and diode-connected QP1, QP2, QP3, and QP4 with their bases connected together, stacking such that the diode-connected side (QN1, QP1, QP3) aligns and connecting the emitter of QP2 to the collector of QP4. Furthermore, the gates of MP1 and MP2 are connected to the collector of QN2 and QP2, respectively. Additionally, the source of MP1 is connected to the drain of MP3 via the source of MP2 and also connected to the source of a Sense MOS. Moreover, the emitter of QP4 is connected to the source of MP4 via R1, and the drain of MP4 is connected to the source (OUT terminal) of a Main MOS. Furthermore, the gates of MP3 and MP4 are connected to the emitters of QN1 and QN2.

Abstract: Apparatuses, devices, and methods for operating a voltage converter are described. A semiconductor device can include a switching circuit and a controller. The switching circuit can include a plurality of switching elements. The controller can determine an operation mode of the switching circuit. In response to the operation mode indicating a two-level operation mode, the controller can program the switching circuit to operate as a two-level voltage converter. In response to the operation mode indicating a three-level operation mode, the controller can program the switching circuit to operate as a three-level converter.

Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

Abstract: A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.

Abstract: Systems and methods for operating a wireless power transfer device are described. A circuit can generate a first signal that indicates a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falling below ground. The circuit can delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The circuit can merge the first signal and the second signal to generate a third signal. A controller can use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. The first LS transistor being turned on at the specific time reduces a diode conduction time of a body diode of the first LS transistor.

Abstract: A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage comprising a comparison circuit configured to receive the reference voltage, receive a feedback voltage, the feedback voltage being dependent on the output voltage, compare the reference voltage and the feedback voltage, and generate an error signal that is dependent on the comparison between the reference voltage and the feedback voltage, a first digital to analog converter configured to be operable in a panic mode in which the first digital to analog converter is configured to receive the error signal, generate a first DAC code signal based on the error signal for a first time period, the output voltage being dependent on the first DAC code signal, and calculate a mean value of the generated first DAC code signal during at least a portion of the first time period, and set the first DAC code signal to the mean value as calculated, a panic circuit configured to detect when the feedback voltage exceeds a fi

Abstract: A driver circuit for controlling a switching element is provided. The driver circuit (200) has a plurality of bootstrap capacitors (210) and a switching unit (211). Furthermore, the driver circuit (200) has a control unit (102) which is configured to control the switching unit (211) in dependence of a control signal (ActHS) to provide a parallel arrangement of the plurality of bootstrap capacitors (210) between a charging voltage (VDD) and a reference voltage, for charging the plurality of bootstrap capacitors (210) during a charging phase; and to provide a serial arrangement of the plurality of bootstrap capacitors (210) between the charging voltage (VDD) and a control port of the switching element (MHS), for controlling the switching element (MHS) during a control phase.

Abstract: A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the digital LDO being synchronized to a clock signal and comprising a first digital to analog converter configured to generate a first DAC code signal, the output voltage being dependent the first DAC code signal, trigger state transitions of the first DAC code signal between states, and for at least a portion of the state transitions of the first DAC code signal, trigger each subsequent state transition after more clock cycles of the clock signal than for the preceding state transition.

Abstract: A current measurement system for a digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the current measurement system comprising a current determination unit configured to receive the first DAC code signal, and generate an output current signal using the first DAC code signal.

Abstract: The present document describes a capacitor circuit (100) which comprises a capacitor element (124) that is arranged between an intermediate node (122) and a reference potential (111), and a switching element (121) which comprises a first terminal that is coupled to the intermediate node (122) and a second terminal that is coupled to the reference potential (111) during the ON state of the switching element (121). Furthermore, the capacitor circuit (100) comprises a control unit (110, 210) which is configured to cause a transition from the ON state to the OFF state of the switching element (121) at a switching time instant; and, within a bias interval that is prior to the switching time instant, to transfer an electrical charge to the intermediate node (122), which is adapted to at least partially compensate an electrical charge that is transferred to the intermediated node (122) during the transition from the ON state to the OFF state of the switching element (121).

Abstract: Systems and methods for demodulating a signal is described. A device can receive a modulated signal that encodes data. The device can sample a voltage of the modulated signal to generate a plurality of samples in digital domain. The device can determine in-phase data and quadrature data of the plurality of samples. The device can determine amplitude data and phase data based on the in-phase data and the quadrature data. The device can decode the amplitude data and phase data into digital symbols that represent the data encoded in the modulated signal.

Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.

Abstract: A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.

Abstract: Systems and methods for evaluating a set of bounding boxes in a blended image are described. A system can include an integrated circuit configured to obtain expected bounding box data. The expected bounding box data can be based on coordinates data of an image. The integrated circuit can determine target coordinates based on the expected bounding box data. The integrated circuit can receive a blended image including a set of objects and a set of bounding boxes. The integrated circuit can extract pixel values located at the target coordinates in the blended image. The integrated circuit can identify an error relating to the set of bounding boxes based on the extracted pixel values and the expected bounding box data.

Abstract: The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.

Abstract: A collision avoidance system includes a periphery monitoring system which detects vehicles in proximity to a subject vehicle by use of a sensor, an approaching vehicle notifying system which communicates with another vehicle in proximity to the subject vehicle in vehicle-to-vehicle communication, and a detected vehicle comparison/determination system which is connected to the periphery monitoring system and the approaching vehicle notifying system, determines common vehicles detected by both the periphery monitoring system and the approaching vehicle notifying system, and controls the periphery monitoring system and the approaching vehicle notifying system.

Abstract: A digital power amplifier to drive an RFID antenna with an antenna signal of a substantial sinusoidal output current. This digital power amplifier includes a switching element built to switch at least one of the 2*W driver blocks from a contributing mode into a none-contributing mode, in which none-contributing mode the driver block does not contribute with an increment of charge to the output current to adjust the amplitude and/or the waveform of the output signal.

Abstract: A disconnection detector circuit that can favorably inspect a connection state of a wire without increase in parasitic capacitance is provided. A semiconductor device includes, in one package, a first integrated circuit including a transformer including a primary coil and a secondary coil, and a second integrated circuit connected to a midpoint and one end of the secondary coil. The second integrated circuit includes a reference line and a detector circuit. The reference line connects the midpoint of the secondary coil and a reference potential. On basis of a potential at a predetermined reference point of the first power supply line, the detector circuit detects whether a connection state between the second integrated circuit and the secondary coil is normal or abnormal.