Abstract: A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.

Abstract: An amplifier assembly suitable for use as a rail-to-rail amplifier is provided. The amplifier assembly includes: a first input circuit connected to a first signal input node for a first input level range; a second input circuit connected to a second signal input node for a second input level range; a load circuit coupled to the first input circuit, the second input circuit and an output node of the amplifier assembly, wherein the first input circuit includes a first auxiliary control transistor element, and a first control transistor element. The first signal input node is coupled to a control terminal of the first control transistor element and a control terminal of the first auxiliary control transistor element. A path connected in parallel to the first control transistor element includes the first auxiliary control transistor element.

Abstract: An apparatus comprising a controller for a switching converter for receiving an input voltage and for providing an output voltage, the switching converter comprising a first switch and an energy storage element, the controller being configured to provide a first control signal to the first switch, the first control signal having a switching frequency, and control the switching frequency such that the switching frequency is substantially unaffected by variations in one or more of a load current, an equivalent series resistance of the energy storage element, and a turn on resistance of the first switch.

Abstract: A comparator is presented. The comparator includes an input port for receiving an input voltage; an output port for providing an output voltage; a resistive divider, first and second transistors, and a differential amplifier. The resistive divider has a first node for providing a first voltage and a second node for providing a second voltage. The first transistor has a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node. The second transistor has a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node. The differential amplifier has a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port.

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a signal cancellation circuit, a sampling circuit, a negative feedback circuit, an AD converter, and an addition-and-subtraction circuit.

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a first switch circuit, a first inversion signal generating circuit, a second capacitive element, and a negative feedback circuit.

Abstract: In an embodiment, an apparatus is disclosed that includes a first battery management circuit. The first battery management circuit is configured to measure a voltage of a first battery cell of a battery pack and to generate a first voltage measurement based at least in part on the measured voltage of the first battery cell. The first battery management circuit is configured to receive a bit of a first response from a second battery management circuit. The bit of the first response is generated by the second battery management circuit based at least in part on a measured voltage of a second battery cell of the battery pack. The first battery management circuit is configured to sum the bit of the first response with a corresponding bit of the first voltage measurement and to provide the summed bit to a third battery management circuit as part of a second response.

Abstract: Described herein is a DC-DC voltage regulator for converting an input voltage at an input port into one or more output voltages at respective output ports.

Abstract: The present document describes a voltage comparator (100) which comprises a differential stage (110) configured to provide a comparator current (203) at an output node (103) of the differential stage (110) in dependence of a first input voltage at a first input node (101) and a second input voltage at a second input node (102) of the voltage comparator (100). The voltage comparator (100) further comprises a current comparator (200) which is configured to provide an output voltage at an output node (206) of the current comparator (200) in dependence of the comparator current (203), and an output stage (220) which is configured to provide an output signal of the voltage comparator (100) in dependence of the output voltage at the output node (206) of the current comparator (200).

Abstract: The present document describes a control circuit (200) for controlling a power converter (100) which is configured to provide at an output node of the power converter (100) an output current (104) at an output voltage (103) based on electrical power at an input voltage (102), which is provided at an input node of the power converter (100).

Abstract: An autonomous power supply switch with a main supply input and a backup supply input and a supply output to supply the power provided at the main supply input and to switch to the backup supply input, if the power at the main supply input is below a switch threshold. The switch includes a first switch transistor connected between the main supply input and the supply output with its gate/base connected to a first steering point of the switch and a second switch transistor connected between the backup supply input and the supply output with its gate/base connected to a second steering point of the switch; an inverter or Schmitt trigger with its input connected to the second steering point and its output connected to the first steering point and its power supply connected to the backup supply input of the switch.

Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. The first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. The second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

Abstract: A semiconductor device includes: a constant current generating circuit unit; a first current mirror circuit unit having a constant current as an input current and generating a first mirror current as a mirror current; a level shift circuit unit including a clamp transistor between whose drain and source a first mirror current flows and to whose base a power supply voltage of the constant current generating circuit unit is applied, and a transistor that is connected in series to the clamp transistor and through which the first mirror current flows; a second current mirror circuit unit having as an input stage a transistor and having as an output stage a transistor through which a second mirror current replicating the first mirror current flows; and an error absorption circuit unit connected to a terminal for outputting the second mirror current of the output-stage transistor in the second current mirror circuit unit.

Abstract: A correction circuit for correcting one or more errors in a digitized current signal, the digitized current signal being a digital representation of an analog current signal of a current flow through an energy storage element, wherein the correction circuit is configured to correct the one or more errors in the digitized current signal by comparing the digitized current signal to the analog current signal, and correcting the digitized current signal based on the outcome of the comparison.

Abstract: A digital controller for a switching converter configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a pulse width modulation control circuit configured to receive the output voltage and to generate a PWM control signal to control the switching operation of the one or more power switches, and switching circuitry configured to couple the pulse width modulation control circuit to the input voltage node during a first phase, and couple the pulse width modulation control circuit to a supply voltage node during a second phase, the supply voltage node being at a supply voltage.

Abstract: A current synthesizer for a switching converter including an energy storage element and a first pass device, the switching converter configured to receive an input voltage and to provide an output voltage, the current synthesizer being configured to determine one or more first properties of a first current path of the switching converter, the first current path comprising the first pass device and the energy storage element, calculate a current flow through the energy storage element using the determined one or more first properties, and generate a digitized current signal, the digitized current signal being a digital representation of the current flow through the energy storage element, as calculated.

Abstract: A digital controller for a switching converter configured to receive an input voltage and to generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller being configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flow through the energy storage element, generate a filtered digital current error signal using the digitized current signal and a ripple cancellation signal, the ripple cancellation signal being arranged to reduce ripple from the digital current signal in the generation of the filtered digital current error signal, and control the switching converter, the control of the switching converter being dependent on the filtered digital current error signal.

Abstract: A digital controller for a switching converter configured to receive an input voltage and to generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a ripple cancellation signal generator configured to generate a ripple cancellation signal, the digital controller being configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flow through the energy storage element, generate a filtered digital current error signal using the digitized current signal and the ripple cancellation signal, the ripple cancellation signal being arranged to reduce ripple from the digitized current signal in the generation of the filtered digital current error signal, and control the switching converter, the control of the switching converter being dependent on the filtered digital current error signal, wherein the ripple cancellation signal, within each signal period, compr

Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.