Patents Assigned to Renesas Technology
  • Semiconductor integrated circuit device
    Patent number: 7696813
    Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: April 13, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Hiroyuki Mizuno
  • Method of manufacturing semiconductor device carrying out ion implantation before silicide process
    Patent number: 7696050
    Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: April 13, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
  • Nonvolatile memory system, semiconductor memory, and writing method
    Patent number: 7697345
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: April 13, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Circuit pattern inspection apparatus
    Patent number: 7696487
    Abstract: The via chain conduction failure due to non-conduction caused by insufficient etching in a contact plug/via plug forming process can be detected precisely in a short time. For its achievement, a defect is detected at high speed by taking advantage of characteristics of a potential contrast method using a via chain defect inspection structure and an electron beam defect detection apparatus which can perform continuous inspection while changing an inspection direction without rotating a wafer. Accordingly, the capturing efficiency of a critical electric defect and search efficiency of a defect point can be improved.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: April 13, 2010
    Assignees: Hitachi High-Technologies Corporation, Renesas Technology Corp.
    Inventors: Koichi Hayakawa, Jiro Inoue, Masaaki Nojiri
  • Semiconductor device and manufacturing method thereof
    Patent number: 7692233
    Abstract: A technology capable of improving a charge retention characteristic of a nonvolatile memory is provided. In a memory cell in which an interlayer insulating film formed of an ONO film obtained by laminating a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film is formed between a floating gate formed of a polycrystalline silicon film and a control gate formed of a polycrystalline silicon film, the upper silicon oxide film is formed through LPCVD and is then nitrided through a remote plasma process, thereby introducing nitrogen of, for example, 5 to 6 atom % into the upper surface portion of the upper silicon oxide film.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kobayashi, Toshiyuki Mine
  • Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
    Patent number: 7692943
    Abstract: A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 6, 2010
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Kenichi Osada, Takayuki Kawahara, Ken Yamaguchi, Yoshikazu Saito, Naoki Kitai
  • Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
    Patent number: 7692234
    Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
  • Display driver and display driving method
    Patent number: 7692641
    Abstract: In a display driver, one scanning period is divided into a period P and a subsequent period D. In the period P, a pre-charge voltage equal to an original data voltage is applied in a time-sharing manner to data lines in one block, and in the period D after the period P, the original data voltage is applied again.
    Type: Grant
    Filed: November 25, 2005
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuyuki Kudo, Akihito Akai, Goro Sakamaki
  • Semiconductor device and method of manufacturing the same
    Patent number: 7692243
    Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Toshiaki Iwamatsu
  • Semiconductor device
    Patent number: 7693000
    Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: April 6, 2010
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd
    Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
  • Data processing apparatus of high speed process using memory of low speed and low power consumption
    Patent number: 7694109
    Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Toyohiko Yoshida, Akira Yamada, Hisakazu Sato
  • Memory card
    Patent number: 7694067
    Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
  • Semiconductor integrated circuit device
    Patent number: 7692997
    Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Masashi Horiguchi, Mitsuru Hiraki
  • Nonvolatile semiconductor memory device having assist gate
    Patent number: 7692966
    Abstract: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kono, Yuichi Kunori, Hironori Iga
  • Method of manufacturing a semiconductor device
    Patent number: 7691677
    Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Semiconductor memory device
    Patent number: 7693004
    Abstract: This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Masaki Tsukude
  • Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film
    Patent number: 7691713
    Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1 (W2/T)<??tan?1 (W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21).
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
  • Semiconductor device
    Patent number: 7692285
    Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yukihiro Sato, Norio Kido, Tatsuhiro Seki, Katsuo Ishizaka, Ichio Shimizu
  • Semiconductor device and a method of manufacturing the same and designing the same
    Patent number: 7687914
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 30, 2010
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Semiconductor device with reduced parasitic inductance
    Patent number: 7687885
    Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: March 30, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima