Abstract: A switching control circuit of synchronous rectification type that is capable of reducing dead time is obtained. Upon detection that an output potential rises above VDD-Va, a first sensor outputs an H signal to a first input terminal of a first NOR circuit, and the first NOR circuit outputs an L signal to a second input terminal of a second NOR circuit, and the second NOR circuit outputs an H signal to a first gate driving circuit. A PMOS is thereby turned on. Upon detection that the output potential falls below GND+Vb, a second sensor outputs an L signal to a first input terminal of a first NAND circuit, and the first NAND circuit outputs an H signal to a second input terminal of a second NAND circuit, and the second NAND circuit outputs an L signal to a second gate driving circuit. An NMOS is thereby turned on.

Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.

Abstract: Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component ?r about a plurality of nodes of the single path is calculated. Next, an on-chip variation component ?chip is calculated on the basis of the on-chip random variation component ?r and an on-chip systematic variation component ?s. Subsequently, a delay variation Docv is calculated on the basis of a reference delay Dbase of the entire path and the on-chip variation component ?chip.

Abstract: Plural inlets 1 are formed by a separation into individual pieces, and these plural inlets are arranged to a tape-like carrier such that the long side of each of the plural inlets is along the longitudinal direction of the tape-like carrier, whereby cost can be reduced by rearranging the inlets to the cheap tape-like carrier. Further, the plural inlets formed by separating into individual pieces are rearranged onto the tape-like carrier, whereby the change of the arrangement pitch of the inlets so as to correspond to the size of a final product at a customer side can be facilitated, and days taken for the development for newly supplying the inlets can be shortened.

Abstract: In a gain switching LNA including a first transistor, a first transistor group (for example, second to ninth transistors) and a second transistor group (for example, tenth to seventeenth transistors), a first resistor connected between an emitter of the tenth transistor and a collector of the first transistor and a second resistor connected to emitters of eleventh to seventeenth transistors and the collector of the first transistor and having a resistance one seventh as high as that of the first resistor are provided. In a high-gain mode, since isolation of the tenth to seventeenth transistors which are turned OFF and the first and second to ninth transistors is secured by the first resistor and the second resistor, there is no deterioration in the noise factor.

Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.

Abstract: A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.

Abstract: The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate.

Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.

Abstract: Disclosed is a direct conversion type transmitter or transceiver circuit suitable for a mobile communication device which corresponds to broad signal output level variable width to be required by W-CDMA, which does not necessitate any high-performance low noise VCO and RF filter, capable of reducing a number of components and the cost. In the input portion of an orthogonal modulator composed of a divider, mixers, and a common load, there are provided variable attenuators. If an input signal level of the orthogonal modulator within the transmitter circuit lowers, this variable attenuator circuit is operated so as to lower the bias of the orthogonal modulator to reduce the amount of occurrence of carrier leak, and to prevent the signal during low output level and carrier leak ratio from being deteriorated.

Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.

Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.

Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.

Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.

Abstract: Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.