Abstract: A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

Abstract: A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

Abstract: A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

Abstract: Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the gate electrode associated with each of the first through third field effect transistors. The sidewall spacers of at least the first field effect transistor have a different width than that of at least the second field effect transistor, the gate electrode of the third field effect transistor has a different length than that of at least the first field effect transistor for memory and the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor.

Abstract: A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first conduction type second well region formed in the first well region; a second conduction type third well region formed in the second well region; a drain region formed in the second well region; a source region formed in the third well region; a gate electrode formed through a gate insulating film over the third well region between the drain region and the source region; and an insulating layer formed between the gate electrode and the drain region. Parasitic capacitances between the semiconductor substrate and the source region and those between the substrate and the drain region are respectively in series.

Abstract: This invention provides a receiver in which the calibration time by repeated operations to correct phase mismatch and amplitude mismatch between I and Q signals can be reduced. The receiver comprises mixers which convert received RF signals into quadrature modulated IF signals, signal paths which filter and amplify and output the quadrature modulated signals output from the mixers, a calibration circuit which calibrates phase and amplitude mismatches between the I and Q components of the quadrature modulated signals output through the signal paths, a frequency converter which, when the mixers or the signal paths selected output calibration signals with IF frequency instead of the quadrature modulated signals, converts the calibration signals into those with a frequency higher than IF frequency, and an arithmetic operation circuit which calculates phase and amplitude mismatches from the calibration signals output by the frequency converter and outputs calculation results.

Abstract: The invention intends to provide a manufacturing method of a semiconductor integrated circuit device, which can detect an off-specification faulty wafer in real time. An abnormality detection server stores apparatus log data outputted from semiconductor manufacturing apparatus that processes a semiconductor wafer in an apparatus log data memory. Thereafter, in a lot end signal receiver, when a lot end signal outputted from the semiconductor manufacturing apparatus is received, an abnormal data detector, after referencing an abnormality detection condition setting file stored in a first detection condition memory, based on the referenced content, judges whether there are abnormal data in the apparatus log data stored in the apparatus log data memory or not. Upon detecting an abnormality, a detection result is outputted to an engineer PC and an operator terminal unit.

Abstract: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

Abstract: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programmed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

Abstract: In radio communication system that is able to transmit in two or more modulation modes, e.g., one modulation mode when phase shifts are performed and another modulation mode when phase shifts and amplitude shifts are performed, the disclosed invention can avoid that receiving band noise becomes so great not to conform to the GSM standards' prescription for such noise in a high voltage region of the power supply voltage, even when the output power is controlled by changing the amplitude of the input signal to the power amplifier circuitry while fixing the bias voltages to be applied to the power amplifying transistors. When the output power is controlled as above, in the modulation mode (GSM mode) when phase shifts are performed, idle currents flowing across the power amplifying transistors are regulated, depending on the power supply voltage, i.e., the idle currents are decreased when the power supply voltage is high and increased when the power supply voltage is low.

Abstract: The invention provides a semiconductor device capable of reducing wasteful power consumption. The semiconductor device of the invention does not require a refresh operation, and includes memory circuits for storing data, arranged in a matrix form, first signal lines for reading data from the memory circuits, second signal lines for transferring a signal that controls connection between the memory circuits and the first signal lines, a sense amplifier circuit for reading and determining data by detecting a potential change or a current change in the first signal lines, and a mitigating means for mitigating the potential change or the current change in the first signal lines during a period in which the sense amplifier circuit is being activated.

Abstract: A data storage circuit having a plurality of memory cells (S1), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the precharge circuit under the control on the basis of a chip enable signal (CE) before write or read of data into/from the memory cells (S1) and in a standby state, the bit lines (BL, /BL) are discharged by the discharge circuit. Further, also in a sleep mode, the bit lines (BL, /BL) are discharged by the discharge circuit. With this circuit configuration and operation, it is possible to provide the data storage circuit which allows reduction in standby power consumption by suppressing standby currents in the standby state.

Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.

Abstract: The frame-memory control-section partitions a frame memory into a plurality of sectors and stores decoded video data of frames not used as predictive video in the frame memory. The frame-memory control-section writes a top-field data and a bottom-field data of the decoded video data into separate free sectors of the frame memory. In reading and displaying the decoded video data from the frame memory, the frame-memory control-section simultaneously releases the sector that stores the top-field data and the sector that stores the bottom-field data during the last display field period of the display video.

Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

Abstract: A control technology for a synchronous motor for suppressing rotational pulsation caused by variation in individuals without making a control algorithm complex is provided. In a motor drive system which is a control device for a synchronous motor, in order to suppress the pulsation component of N times as high as the AC frequency for driving the synchronous motor, a controller in which the phase property of the disturbance response of the controller with respect to the pulsation frequency is within ±45° is arranged. Therefore, the torque pulsation component generated from distortion in induction voltage or variation between phases is suppressed.

Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.

Abstract: An IC card 1CD includes a frame member portion 1CB1, and an IC card main body 15 held in a state of being hung by a connecting portion 1CB2 in a frame thereof. The IC card main body 15 is made to constitute a card type information medium having a high functional performance having both of a function as a so-to-speak IC card and a function as a so-to-speak memory card having a capacity larger than that of the IC card and a function higher than that of the IC card capable of executing a security processing. An outer shape of the IC card main body 15 is formed in compliance with RS-MMC outer shape standard. A surface of a cap portion 1CB3 of the IC card main body 15 is printed with a desired character, pattern, diagram and photograph or the like by a printing method used in steps of fabricating a general IC card, and the IC card 15 is provided with higher acknowledgement performance, security performance and outlook.

Abstract: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a source lead S1, and a drain lead D2 are arranged from left to right on the first surface of the package and a drain lead D1, a source lead S2, and a gate lead G2 are arranged from left to right on the second surface. A gap between the source lead S1 and the drain lead D2 is two times a gap between the gate lead G1 and the source lead S1, and a gap between the drain lead D1 and the source lead S2 is two times a gap between the source lead S2 and the gate lead G2.