Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

Abstract: A semiconductor integrated circuit device (IC) and a contactless IC card including a receiver circuit that is able to stably demodulate information signals superimposed on AC signals from an interrogator. The receiver circuit included in the IC is equipped with antenna terminals, a power supply circuit, and a filter circuit. The information signal from which a high frequency component was eliminated through the filter circuit is input via a capacitor to an inverting input terminal of an operational amplifier and a reference voltage is input to a non-inverting input terminal thereof. After the information signal is fed back through a feedback path to the non-inverting input terminal of the operational amplifier, that signal is amplified and the amplified information signal is binarised by a binarising circuit, thereby data transmitted from the interrogator is demodulated. The contactless IC card comprises an antenna coil and the IC including this receiver circuit.

Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.

Abstract: The invention provides a signal processing semiconductor integrated circuit of the direct conversion system, which includes a dummy amplifier having the same circuit configuration as a low noise amplifier being the first stage amplifier, in which the DC offset calibrations on the subsequent stage amplifiers are carried out during shifting into the reception mode in a state that the low noise amplifier is deactivated and the dummy amplifier is activated. Thereby, the invention achieves to suppress generation of the DC offsets resulting from the leakage noises of the local oscillator during shifting into the reception mode, and to enhance the reception sensitivity.

Abstract: A non-volatile memory device is provided which includes a flash memory having a plurality of banks and a bank selection register which can take on states at least equal in number to the number of banks. The bank selection register outputs a signal to point to one of the banks based upon one of the states of the bank selection register. A controller is also provided having a plurality of data buffers corresponding, respectively, to the banks. In addition to word lines, bit lines and memory cells, each bank includes a data register to temporarily hold data to be written to the memory cells. The controller transmits data in the data buffer to the data register of the pointed to bank, while the flash memory writes data held in the data register to the memory cells of another one of the banks.

Abstract: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.

Abstract: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si for the barrier film increasing the contact resistance to n-Si and backwardly biasing the emitter and base of a parasitic bipolar transistor making it less tending to turn-on, thereby decreasing the leak current of power MISFET.

Abstract: An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to reach the buried oxide film, so parasitic capacitance is reduced. This structure achieves an SOIMOS transistor capable of reducing junction capacitance at low drain voltage.

Abstract: A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.

Abstract: A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.

Abstract: There is provided semiconductor memory capable of reconfiguring an area to be given an authentication key and access limitation, and there is implemented an information distribution system having an advanced security function using the semiconductor memory. Part of a storage area in the semiconductor memory stores information about the area to be given the authentication key and the access limitation. Alternatively, the authentication key is stored in units of data to be authenticated for limiting an access to stored information. Information is protected doubly by storing encrypted information in the area provided with the access limitation according to the above-mentioned method.

Abstract: A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations.

Abstract: A semiconductor device includes a wiring board, a first semiconductor chip (e.g. DRAM) that is flip-chip connected on the wiring board, a second semiconductor chip (e.g. DRAM) that is of the same type as the first semiconductor chip and is mounted face up on the first semiconductor chip such that the orientation of the arrangement of the pads is at 90° from that of the first semiconductor chip, a third semiconductor chip (e.g. microcomputer chip) disposed on the second semiconductor chip, wires, and a sealing medium. The wiring board has a plurality of common wiring patterns for electrically connecting first electrodes for the first semiconductor chip and second electrodes for the second semiconductor chip. The common wiring patterns can be disposed without crossing on the surface wire layer of the wiring board.

Abstract: When a transmitting oscillator is built in a communication semiconductor integrated circuit device like a high-frequency IC constituting a wireless communication system, the system prevents degradation of the accuracy of control on the output power of a power amplifier due to noise jumped from an output pin of the transmitting oscillator to an input pin for a detected signal (feedback signal) of an output level of the power amplifier. The transmitting oscillator is built in the high-frequency IC. The detected signal of the output level of the power amplifier, which is detected by a coupler, is attenuated to a level slightly higher than the level of noise jumped from the output pin of the transmitting oscillator to the input pin for a feedback signal of an amplitude control loop, which in turn is inputted to the feedback signal input pin of the high-frequency IC.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: Each of switching circuits included in each of semiconductor memory chips performs switching among interface functions of predetermined second external connecting electrodes by bonding options in accordance with states of potentials applied to first external connecting electrodes. The second external connecting electrodes intended for interchange of the interface functions are electrodes for plural-bit parallel input/output and electrodes for the input of control signals. For example, the switching circuit interchanges interface functions among the predetermined second external connecting electrodes and switches between valid and invalid states of the interface functions of the predetermined second external connecting electrodes.

Abstract: An image pickup control unit specifies a scan area of a frame based on a scaling factor for electronic zooming. An image sensor converts incoming light signals into electric signals by performing reset scanning on each line of the specified scan area of the frame, and accumulates each of the electric signals, and reads the electric signals accumulated thereby by performing read scanning to output them as image data. In response to an instruction for changing a horizontal scanning period and a vertical scanning period of an Nth frame and later frames in a series of frames from the image pickup control unit, the image sensor performs reset scanning and read scanning on the Nth frame based on the changed horizontal scanning and vertical scanning periods even when a reset scanning period of the Nth frame partially overlaps a read scanning period of an immediately preceding (N?1)th frame.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: A data processor having: an instruction fetch unit for acquiring an instruction; and an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit. In the data processor, the instruction execution unit includes an execution pipeline pipelined into two or more stages for execution of the execution instruction, and an execution pipeline control unit capable of changing a stage to arrange an operation by the execution unit in according to the number of wait cycles until data required for execution of the execution instruction is fixed. The stage, where an operation by the execution unit is arranged, is changed according to the number of wait cycles until the data is fixed, whereby the number of input-fixing wait cycles increased by pipelining cache access can be reduced.