Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.

Abstract: Each of program cell and memory cells includes a magnetic storage portion of the same configuration. The program cell further includes a state change portion. That is, the program cell has the same structure as the memory cell, except that the state change portion is additionally provided thereto. As such, the program cell can be provided efficiently, as it can be designed the same as the memory cell in terms of the magnetic storage portion and others. The state change portion makes a transition to a fixed state based on an electrical change. Thus, the state change portion prevents program information from being rewritten by a magnetic noise or the like, and ensures stable storage of the program information.

Abstract: A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).

Abstract: An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.

Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Abstract: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

Abstract: In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.

Abstract: A wireless communication system has a first operation mode (GSM mode) for amplifying a phase-modulated high frequency signal with a high frequency power amplifier circuit and a second operation mode (EDGE mode) for amplifying a phase and amplitude-modulated high frequency signal with the amplifier circuit. The amplifier circuit has an input of a high frequency signal, with the amplitude and frequency being fixed in both the first and second operation modes, and operates by being controlled for the bias state of each amplifying stage in accordance with the output control signal produced by a control circuit based on the demanded output level (Vapc) and the detected output level (VSNS) so that the amplifier circuit performs signal amplification to meet the demanded output level.

Abstract: Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

Abstract: A method of manufacturing a thin, small-sized, inexpensive, non-leaded, resin-sealed type semiconductor device is disclosed. A flexible tape having plural terminals peelably through a first adhesive in a product forming portion formed on a main surface of the tape is provided, a semiconductor element is fixed to the main surface of the tape peelably through a second adhesive, electrodes formed on the semiconductor element and the terminals are connected together through conductive wires, an insulating resin layer is formed in an area including the semiconductor element and the wires on the main surface of the tape to cover the semiconductor element and the wires, and the tape on a back surface of the insulating resin layer is peeled, allowing the terminals to be exposed to the back surface of the insulating resin layer. Exposed surfaces of the terminals are each formed by a gold layer.

Abstract: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

Abstract: An imaging control unit specifies a scan region, including an effective pixel region and a blanking region, of an image based on a magnification for electronic zooming, and converts an input optical signal into an electrical signal by scanning the scan region. The imaging control unit reads the electrical signal stored and delivers the electrical signal to an image sensor unit as picture data. An RW control unit stores the picture data in a register based on the magnification for electronic zooming, and then reads the picture data at a predetermined frame rate. A resolution converter performs interpolation processing of the picture data based on the magnification for electronic zooming.

Abstract: A transmission oscillator of differential output configuration is incorporated into a high frequency IC. Further, an equivalent impedance having an impedance equivalent to the impedance connected with a regular output terminal is provided. Or, a dummy external terminal for outputting transmit signals in opposite phase is provided. One of the differential outputs of the transmission oscillator is inputted to the power amplifier through the regular output terminal. The other of the differential outputs is connected to the equivalent impedance or the dummy external terminal.

Abstract: The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access rights, and an arbitration control logical unit for arbitrating the access rights of the master circuits based on the information. When the priority of the first master circuit is higher than the priority of the second master circuit and there is no access request from the first master circuit but there is an access request from the second master circuit, the arbitration control logical unit permits access of the second master circuit, and the storage units lower the priority of the second master circuit without changing the priority of the first master circuit.

Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

Abstract: The present invention provides a high frequency power amplifier circuit capable of obtaining sufficient detection output even in a range where a request output power level is low and performing a desired output power control by a control loop with the detection output in a radio communication system which detects output power and performs feedback control. An output power detection circuit which detects the level of output power on the basis of an AC signal supplied from a final amplification stage of a high frequency power amplification circuit via a capacitive element has a circuit configuration such that in a state where the output power control voltage is lower than a certain level, current (Isu) according to the output power control voltage is generated and supplied to the output power detection circuit, and detection sensitivity of the output power detection circuit improves according to the current.

Abstract: An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

Abstract: An orthogonal modulating circuit for modulating signals of two oscillation frequencies differing in phase by 90° with transmission data (I and Q) is used in common for a plurality of bands, an LC resonance circuit comprising inductances L and a capacitor C is used as the output load on the orthogonal modulating circuit instead of resistors commonly used according to the prior art, and the values of L or C constituting the resonance circuit are switched over between each other according to the transmission band.

Abstract: A high frequency power amplifier circuit includes amplifying devices whose control terminals (gate or base terminals) are supplied with a bias voltage. The high frequency power amplifier circuit keeps constant the bias voltage so that the amplifying devices operate in a saturation region. The high frequency power amplifier circuit controls an operating power supply voltage supplied to the amplifying devices in accordance with an output request level to control output power. A device (diode) having temperature dependency is provided for an operating power supply voltage control circuit that controls the operating power supply voltage for the amplifying devices in accordance with the output request level. The operating power supply voltage control circuit is configured to generate the operating power supply voltage corresponding to the device's temperature characteristics and supply it to the amplifying devices.

Abstract: Enhanced functionality is provided in memory devices by enhancing the control logic to recognize predetermined data sequences. Standard (legacy) device operations are used to communicate the predetermined data sequences, thereby allowing existing device drivers to be used with the enhanced devices.