Abstract: The detector includes a plug for connecting a personal computer through a cable, a battery power supply which provides a constant power supply, and an MCU which receives a specific potential from the personal computer when the latter is connected.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se

Abstract: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.

Abstract: A driving circuit supplies a suppression current (I4) which reduces a decrease in a driving current (Idrive) immediately after occurrence of an overshoot at the time of the rise of the driving current (Idrive) to a laser diode (1). The driving circuit draws a suppression current (I5) which reduces an increase in the driving current (Idrive) immediately after occurrence of an undershoot at the time of the fall of the driving current (Idrive) from the driving current (Idrive).

Abstract: Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

Abstract: In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other.

Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

Abstract: In remote plasma cleaning, it is difficult to locally excite a plasma because the condition is not suitable for plasma excitation different from that at the time of film formation and a method using light has a problem of fogginess of a detection window that cannot be avoided in a CVD process and is not suitable for a mass production process.

Abstract: Disclosed is a semiconductor IC device using a low-price oscillator, which is capable of bidirectional communication with a host and features a low price. In bidirectional communication between a host and a device, the device comprises a synchronization establishment unit, a frequency difference detector, a frequency generator, and an oscillator providing a reference signal. The synchronization establishment unit to which an output signal from the host is inputted outputs a received signal, a synchronization establishment signal and a reception data. The frequency difference detector detects a frequency difference between a received signal and a transmitting signal, and outputs a frequency coordination signal to the frequency generator. The number of frequency division of the frequency generator is controlled by the frequency coordination signal, and the frequency generator is capable of matching the frequency of the transmitting signal which is an output signal with the frequency of the received signal.

Abstract: The semiconductor device concerning the present invention has a wiring substrate, a semiconductor chip, under-filling resin, a reinforcement ring, a heat spreader, a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out by a clearance region, an insulating film, a wiring layer via land, a via, and a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip. The wiring layer via land is formed between the semiconductor chip and the reinforcement ring, and within a region of a 1 mm width from the extension line of the diagonal line of the semiconductor chip. The angle of the lead-out direction of the wiring from a wiring layer via land to the extension line of the diagonal line of the semiconductor chip is 20° or more.

Abstract: A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

Abstract: The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract: In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, and therefore, the data read speed can be increased.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.