Abstract: A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed.

Abstract: A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet.

Abstract: The present invention is a receiving circuit used for a cellular phone that is reduced in size and can realize low power consumption. In a signal reception circuit that is used in a cellular phone that perform transmission and reception of a plurality of band wireless signals and includes a low-pass filter for removing blockers unnecessary for signal reception, the low-pass filter 104 is composed of a plurality of filters composed of a plurality of different circuit configurations and having a plurality of different pole positions, switching between a filter for blocker removal and a filter configuration with reduced sensitivity degradation is performed by combining a plurality of filters for each signal reception band, and by performing power-off of an unnecessary filter portion in the filter configuration, power consumption is reduced.

Abstract: Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball.

Abstract: A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

Abstract: The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: An exemplary method is disclosed to accurately estimate the center frequency of a narrow-band interference (NBI). The exemplary method uses multi-stage autocorrelation-function (ACF) to estimate an NBI frequency. The exemplary method allows an accurate estimation of the center frequency of NBI in an Ultra-Wideband system. A narrow band interference (NBI) estimator based on such a method allows a low complexity hardware implementation. The exemplary method estimates the frequency in multiple stages. Each stage performs an ACF operation on the received signals. The first stage gives an initial estimation and the following stages refine the estimation. The results of all stages are combined to produce the final estimation. An apparatus based on such a multi-stage narrow band interference frequency detector is also disclosed to improve the accuracy by combining various filters with the detector.

Abstract: A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell.

Abstract: The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Abstract: A liquid crystal display device comprises a liquid crystal display panel and a semiconductor integrated circuit for driving and controlling the liquid crystal display panel. The number of input/output wires connected to I/O terminals (bonding pads) of the semiconductor integrated circuit is reduced so as to simplify wiring patterns of the I/O wires, whereby degrees of freedom in arranging the I/O wiring patterns are enhanced. The panel has a pair of insulating substrate, and the semiconductor integrated circuit is mounted on one of the paired substrates. The semiconductor integrated circuit has a mode terminal which is fixed to a power supply potential or to a reference potential during operation of the integrated circuit, and power supply dummy terminals connected to the power supply potential or reference potential inside the semiconductor integrated circuit. The wiring patterns formed on the paired insulating substrates connect the mode terminal to the power supply dummy terminals.

Abstract: The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.

Abstract: A technique of frequency hopping communication capable of high-speed switching of a plurality of signals having ultra-wide band 528 MHz bandwidth at high-speed and setting and switching a band center frequency and the number of bands arbitrary is provided. A radio transceiver has a frequency hopping communication function of UWB system for switching the ultra wide band signal. In the device, high-speed frequency hopping is realized by controlling an SSB mixer in a local oscillator circuit and switching the frequency of a DDS. The device sets NCO data to the DDS and switches a quadrature phase signal of an output, and switches a signal input of an input terminal of the SSB mixer by a control of a phase switching switch. One of a sum component and a difference component of a mixture of first and second quadrature phase signals is outputted from the output terminal of the SSB mixer.

Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.

Abstract: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

Abstract: A switching power supply capable of correcting a power factor without using a shunt resistor is provided. The switching power supply includes a rectifier for rectifying an AC power supply, boosting means including a power MOSFET for boosting an output of the rectifier, a smoothing capacitor for smoothing an output of the boosting means, voltage-dividing resistors for detecting a voltage between main terminals of the power MOSFET, a switch for selecting only the voltage by which the power MOSFET is in on-state from voltages detected by the voltage-dividing resistors, an amplifier for amplifying the voltage selected by the switch and outputting the same as a current corresponding value of a current flowing in the power MOSFET, voltage-dividing resistors for detecting the output voltage, and driving means which form a pulse signal based on the current corresponding value and the output voltage for driving the power MOSFET by the pulse signal.

Abstract: A method and system for providing a magnetic element and memory utilizing the magnetic element are described. The magnetic element includes a reference layer, a nonferromagnetic spacer layer, and a free layer. The reference layer has a resettable magnetization that is set in a selected direction by a magnetic field generated externally to the reference layer. The reference layer is also magnetically thermally unstable at an operating temperature range and has KuV/kBT is less than fifty five. The spacer layer resides between the reference layer and the free layer. In addition, the magnetic element is configured to allow the free layer to be switched to each of a plurality of states when a write current is passed through the magnetic element.

Abstract: A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.

Abstract: A semiconductor device which stores a plurality of semiconductor chips, having planar sizes which differ, in the same sealing body in a state in which they are accumulated via an insulating film which has an adhesive property. In the semiconductor device, the thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit is formed is thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit is formed.