Abstract: A semiconductor device includes a semiconductor layer, first and second trenches extending into the semiconductor layer, an insulating layer on the semiconductor layer, a first electrode in the first trench, and a second electrode in the second trench. The second electrode is electrically insulated from the first electrode. Contact plugs extend through the insulating layer and contact the semiconductor layer. The first and second trenches extend in a first direction. The first trench is separated from the second trench in a second direction orthogonal to the first direction. The semiconductor layer includes a mesa between the first trench and the second trench. The contact plugs include a contact plug row in contact with the mesa. The contact plug row overlaps the second trench in plan view and is separated from the first trench. The contact plugs in the row are spaced apart in the first direction.

Abstract: The semiconductor device includes a semiconductor layer having an active portion and a gate finger portion, an MIS transistor formed at the active portion including a gate trench and a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.

Abstract: A semiconductor substrate disclosed herein includes: an SiC single crystal substrate; a graphene layer disposed on an Si plane of the SiC single crystal substrate; an SiC epitaxial growth layer disposed above the SiC single crystal substrate via the graphene layer; and a polycrystalline Si layer disposed on an Si plane of the SiC epitaxial growth layer. The semiconductor substrate may include a graphite substrate or an silicon substrate disposed on a polycrystalline Si layer. The semiconductor substrate may include an SiC polycrystalline growth layer disposed on a C plane of the SiC epitaxial growth layer.

Abstract: A successive approximation register A/D converter (SARADC) has redundancy. An analog unit samples an analog input voltage and generates a comparison signal indicating a magnitude relationship between a threshold voltage corresponding to a control code and the analog input voltage. A logic unit generates, in an i-th (i?1) cycle, a first value obtained by adding a weight of an (i+1)-th cycle to a control code of the i-th cycle and a second value obtained by subtracting the weight of the (i+1)-th cycle from the control code of the i-th cycle. When a comparison signal of the cycle is determined, the logic unit supplies one of the first value and the second value corresponding to the comparison signal to the analog unit 110 as a control code of the (i+1)-th cycle.

Abstract: A semiconductor device includes: a semiconductor layer having a partitioned region partitioned by a trench; a field insulating layer which is formed on a main surface of the semiconductor layer at an interval from the trench toward an inner side of the partitioned region and covers the partitioned region; a trench insulating layer formed at least in the trench; an intermediate region annularly formed between the field insulating layer on the main surface of the semiconductor layer and the trench insulating layer; and a bridge insulating layer which is formed in the intermediate region and connects the field insulating layer and the trench insulating layer, wherein the bridge insulating layer has a bridge buried portion buried in the main surface of the semiconductor layer.

Abstract: A power control device serves as a main controlling agent in a power supply device which generates an output voltage from an input voltage using an output transistor, and includes: an output feedback circuit configured to receive the output voltage or a feedback voltage corresponding to it to generate a driving signal for the output transistor; a current feedback signal generation circuit configured to generate a current feedback signal for adjusting the phase characteristics of the output feedback circuit according to an output current of the power supply device; and a delay circuit configured to delay a change in the current feedback signal in response to a change in the output current.

Abstract: A semiconductor device includes a semiconductor chip that has a main surface, and a field insulating film that partially covers the main surface and has an insulating side wall in which an inclined angle made with the main surface is not less than 20° and not more than 40°.

Abstract: A semiconductor device includes: a semiconductor chip including a first main surface on one side and a second main surface on the other side; a pn junction portion extending along the first main surface and formed inside the semiconductor chip; a trench configured to penetrate the pn junction portion from the first main surface and partition an element region in the semiconductor chip; an insulating film configured to cover a side wall and a bottom wall of the trench; and an embedded electrode embedded in the trench via the insulating film, wherein the bottom wall of the trench includes a protrusion protruding from a lower end of the insulating film toward an inner upper side of the insulating film in a depth direction of the trench.

Abstract: This semiconductor device is provided with: a semiconductor layer; an insulating film which is formed on the surface of the semiconductor layer; a main cell region which comprises a main cell, while being provided in the semiconductor layer; and a temperature-sensing diode for sensing the temperature, the diode being provided in a region other than the main cell region. The temperature-sensing diode comprises a diode cell which is composed of: a first semiconductor region of a first conductivity type; and a second semiconductor region of a second conductivity type. The second semiconductor region is formed into a ring shape so as to surround the first semiconductor region. The inner lateral surface of the second semiconductor region is joined with the first semiconductor region.

Abstract: The present disclosure provides a semiconductor element, which is a switching element. The switching element includes an element front surface on which a gate pad, a plurality of drain pads, and a plurality of source pads are disposed. A source area which is the total area of the plurality of source pads, is larger than a drain area, which is the total area of the plurality of drain pads.

Abstract: A nitride semiconductor device includes an electron transport layer, an electron supply layer, a gate layer including an acceptor impurity, a gate electrode over the gate layer, a passivation layer, a source electrode and a drain electrode. The source electrode includes a field plate section that covers the gate layer and the gate electrode. The field plate section includes a field plate end section that is positioned between the gate layer and the drain electrode. The electron supply layer includes a first recess that is formed in the top surface of the electron supply layer, and that overlaps the gate layer in a plan view, and a second recess that is formed in the top surface of the electron supply layer, and that overlaps the field plate end section in a plan view.

Abstract: A semiconductor device includes a chip, a drain region, a source region formed at the surface layer portion of the main surface at a distance from the drain region, a channel inversion region formed on a side of the source region between the drain region and the source region in the surface layer portion of the main surface, a drift region formed in a region between the drain region and the channel inversion region in the surface layer portion of the main surface, a gate insulating film having a first portion that covers the channel inversion region on the main surface and a second portion that covers the drift region on the main surface, and a gate electrode having a first electrode portion covering the first portion and a second electrode portion led out from the first electrode portion onto second portion so as to partially expose second portion.

Abstract: A semiconductor device capable of suppressing separation of a sealing resin at an internal reverse surface is provided. The semiconductor device includes a semiconductor element, a first lead on which the semiconductor element is mounted, and a sealing resin covering the semiconductor element and a part of the lead. The lead includes an obverse surface to which the semiconductor element is bonded, a reverse surface facing away from the obverse surface in a thickness direction of the first lead and exposed from the sealing resin, and an internal reverse surface facing the same side as a side that the reverse surface faces in the thickness direction and covered with the sealing resin. The internal reverse surface includes an irregular portion.

Abstract: A semiconductor device includes a semiconductor substrate, a first electroconductive member that is formed on the semiconductor substrate and that has a first linear portion extending along a principal surface of the semiconductor substrate, and an organic insulation layer that is formed on the semiconductor substrate and that covers the first electroconductive member, and the first linear portion includes a first side edge portion formed by a curve that is alternately bent to one side and to an opposite side of a direction intersecting a longitudinal direction of the first linear portion in a plan view.

Abstract: A voltage detection circuit includes: a self-bias unit, generating a self-bias voltage based on a reference voltage; and detection units, comparing magnitudes of each voltages as a detection target and a reference voltage, and outputting first to nth voltage detection signals indicating whether the voltage is higher than the reference voltage. Each detection units includes: fifth and sixth transistors, respective drains being connected, and, with respective gates receiving one of the voltages, the fifth and sixth transistors outputting a voltage generated at the respective drains as one of the voltage detection signals; seventh and eighth transistors, respectively supplying a current corresponding to the self-bias voltage to the fifth and sixth transistors. The voltage detection circuit includes a current source transistor, causing an operating current based on a bias voltage received by the gate to flow through the self-bias unit and the detection units.

Abstract: A display driver and a display device including the same include multiple circuit blocks, each of which generates a signal representing, through time division multiplexing, voltage values corresponding to brightness levels indicated by respective K pixel data pieces as a drive signal, and generates first to Qth pixel data signals representing the K pixel data pieces with Q signals by time division multiplexing at least one pair of pixel data pieces consisting of two data pieces from among the K pixel data pieces. Each of the circuit blocks converts the first to Qth pixel data signals into first to Qth gradation voltages, for each of horizontal scanning periods, generates a gradation voltage signal representing, through time division multiplexing, voltage values corresponding to the respective K pixel data pieces expressed by the first to Qth gradation voltages, and outputs a signal amplified from the gradation voltage signal as the drive signal.

Abstract: The present disclosure provides a state detection device, which is designed in a power supply circuit including a feedback control unit configured to perform feedback control based on a difference between a feedback voltage corresponding to an output voltage and a reference voltage; and an output capacitor configured to smooth the output voltage. The state detection device is configured to detect a state of the output capacitor. The state detection device includes target value varying unit and a detector. The target value varying unit is configured to increase a target value of the output voltage. The detector is configured to detect the state of the output capacitor based on a change in the output voltage while the output capacitor is being charged as the target value of the output voltage rises or while the output capacitor is being discharged after the target value of the output voltage rises.

Abstract: Provided is a MEMS device including a substrate that has a first principal surface and a second principal surface facing the first principal surface, and in which a cavity recessed from the first principal surface side to the second principal surface side is disposed, and a MEMS electrode that is disposed within the cavity, and that is separated from a bottom surface of the cavity to the first principal surface side. The MEMS includes a movable electrode finger, a fixed electrode finger, a beam portion, and an electrode portion. The electrode portion includes a first electrode finger and a second electrode finger.

Abstract: A power supply control circuit includes: a soft start generation circuit that outputs a soft start voltage which gradually increases with time; an error signal generation circuit that generates an error signal corresponding to a difference between a feedback voltage corresponding to an output voltage in a switch output stage and the soft start voltage; an output control circuit that controls the switch output stage according to the error signal; and a soft start control circuit that controls the soft start voltage according to the feedback voltage.

Abstract: A nitride semiconductor device includes a semiconductor substrate, an electron transit layer, an electron supply layer, a gate layer, a gate electrode, a source electrode, and a drain electrode. The nitride semiconductor device includes a cell region in which a transistor, including the gate electrode, the source electrode, and the drain electrode, is arranged. A peripheral region surrounds the cell region in plan view. A nitride semiconductor layer, formed from a nitride semiconductor including an acceptor impurity, is located in the peripheral region. A second peripheral electrode is located above the nitride semiconductor layer. A first peripheral electrode is located in the peripheral region. The first peripheral electrode is electrically connected to the gate electrode. The second peripheral electrode is electrically connected to the source electrode.