Patents Assigned to ROHM Co., Ltd.
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Publication number: 20250048722Abstract: The present disclosure provides a semiconductor device including a diode. The semiconductor device includes: a semiconductor substrate; an n-type diffusion region selectively formed in a surface layer portion of a p-type epitaxial layer; an n-type buried layer sandwiched between the semiconductor substrate and the n-type diffusion region and having an impurity concentration greater than that of the n-type diffusion region; a p-type anode contact region formed in a surface layer portion of a first main surface of the semiconductor substrate; an n-type first cathode contact region formed in a surface layer portion of the n-type diffusion region and in a surface layer portion of the first main surface; a p-type well region extending along a depth direction from the first main surface outside the first cathode contact region to reach the n-type buried layer, dividing the n-type diffusion region along a direction along the first main surface.Type: ApplicationFiled: July 30, 2024Publication date: February 6, 2025Applicant: ROHM CO., LTD.Inventors: Shoji TAKEI, Yuji KOGA
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Publication number: 20250046657Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.Type: ApplicationFiled: October 21, 2024Publication date: February 6, 2025Applicant: ROHM CO., LTD.Inventors: Masatoshi AKETA, Kazunori FUJI
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Publication number: 20250048672Abstract: A semiconductor device includes: a semiconductor chip having a first main surface and a second main surface opposite to the first main surface; a first drain region of first conductivity type formed in a surface layer portion of the first main surface; a back gate region of second conductivity type spaced apart from the first drain region in the surface layer portion of the first main surface; a source region of the first conductivity type spaced inward from a peripheral edge of the back gate region in a surface layer portion of the back gate region; a back gate contact region of the second conductivity type electrically isolated from the source region in the surface layer portion of the back gate region; and a gate electrode facing a channel region formed in the back gate region between the peripheral edge of the back gate region and the source region.Type: ApplicationFiled: July 30, 2024Publication date: February 6, 2025Applicant: ROHM CO., LTD.Inventors: Shoji TAKEI, Yuji MATSUMOTO
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Publication number: 20250048685Abstract: A semiconductor device includes: a semiconductor chip having a main surface; an output region formed over the main surface with output elements being arranged in the output region; an inner element region surrounded by the output region and insulated and isolated from the output region with a first element different from the output elements being arranged in the inner element region; a first wiring layer formed over the main surface so as to cover the output region, and including a first output wiring electrically connected to the output elements; and a second wiring layer formed over the first wiring layer, and including second output wirings electrically connected to the first output wiring and a connection wiring insulated and isolated from the second output wirings, the connection wiring extending across the output region from the inner element region to an outer region outside the output region.Type: ApplicationFiled: August 1, 2024Publication date: February 6, 2025Applicant: ROHM CO., LTD.Inventor: Yuji OSUMI
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Publication number: 20250046732Abstract: The present disclosure provides a method for manufacturing a semiconductor device, comprising: a first process of forming a first layer on a main surface of a wafer, wherein the first layer has a reference mark for measuring a positional deviation of a resist relative to a first element pattern for a semiconductor element; a second process of forming the resist on the first layer to cover the reference mark and the first element pattern; a third process of exposing and developing the resist to form a positional deviation determination pattern overlapping the reference mark in a plan view; a peripheral pattern surrounding the positional deviation determination pattern in the plan view; and a second element pattern for the semiconductor element; and a fourth process of determining a positional deviation of the second element pattern with respect to the first element pattern.Type: ApplicationFiled: July 30, 2024Publication date: February 6, 2025Applicant: ROHM CO., LTD.Inventor: Ryuta KIMURA
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Publication number: 20250046632Abstract: A heat treatment apparatus includes a semiconductor substrate; a carbon susceptor on which the semiconductor substrate is placed; a first heating device; an optical system for condensing light output from the first heating device and irradiating the surface of the semiconductor substrate; and a second heating device which faces the semiconductor substrate across the carbon susceptor and is arranged at a distance from the carbon susceptor. The semiconductor substrate is heated to a first temperature by the second heating device; and the semiconductor substrate is heated to a second temperature higher than the first temperature by the first heating device with the optical system that condenses light and irradiates the semiconductor substrate.Type: ApplicationFiled: October 25, 2024Publication date: February 6, 2025Applicant: ROHM CO., LTD.Inventors: Makoto TAKAMURA, Keiju SATO
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Patent number: 12218620Abstract: A motor driver circuit includes: an error detection amplifier configured to receive a current feedback signal indicating a drive current of a motor as an object to be driven and an analog command signal indicating a target amount of the drive current, and generate an analog error signal indicating an error between the drive current and the target amount of the drive current; an A/D converter configured to convert the analog error signal generated by the error detection amplifier into a digital error signal; a digital compensator configured to generate a digital control amount based on the digital error signal output by the A/D converter; a D/A converter configured to convert the digital control amount into an analog control signal; and an output stage configured to supply a drive signal according to the analog control signal to the motor.Type: GrantFiled: November 2, 2022Date of Patent: February 4, 2025Assignee: ROHM CO., LTD.Inventor: Hisashi Sugie
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Patent number: 12214676Abstract: A switching power supply device includes a first switch, a second switch, a current sensing portion configured to sense current flowing in the second switch, and a controller configured to control the first and second switches in accordance with the current sensed by the current sensing portion. The controller includes an accumulating portion configured to accumulate information of the current sensed by the current sensing portion during a predetermined period of time while the first switch is in the off state, and reflecting portion configured to start the transmission of the current information accumulated by the accumulating portion before the first switch is changed from the off state to the on state so as to reflect the current information accumulated by the accumulating portion on the slope voltage, and controls the first and second switches in accordance with the slope voltage.Type: GrantFiled: July 13, 2021Date of Patent: February 4, 2025Assignee: Rohm Co., Ltd.Inventor: Yuhei Yamaguchi
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Patent number: 12218187Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.Type: GrantFiled: February 22, 2023Date of Patent: February 4, 2025Assignee: ROHM CO., LTD.Inventors: Yuki Nakano, Masaya Ueno, Sawa Haruyama, Yasuhiro Kawakami, Seiya Nakazawa, Yasunori Kutsuma
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Patent number: 12217913Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a capacitor portion and a substrate body portion. The capacitor portion includes a plurality of wall portions having a lengthwise direction and separated from each other by a trench formed on a first main surface of the substrate. The substrate body portion is formed around the capacitor portion using a portion of the substrate. The plurality of wall portions are formed of a plurality of pillar units. The capacitor portion, in the plan view, includes a first capacitor portion and a second capacitor portion. The first capacitor portion includes the plurality of wall portions having the lengthwise direction as a first lengthwise direction. The second capacitor portion includes the plurality of wall portions having the lengthwise direction as a second lengthwise direction orthogonal to the first lengthwise direction.Type: GrantFiled: September 22, 2022Date of Patent: February 4, 2025Assignee: ROHM CO., LTD.Inventor: Keisuke Fukae
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Patent number: 12218123Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.Type: GrantFiled: September 20, 2022Date of Patent: February 4, 2025Assignee: ROHM CO., LTD.Inventor: Keisuke Fukae
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Patent number: 12218234Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.Type: GrantFiled: August 2, 2023Date of Patent: February 4, 2025Assignee: ROHM CO., LTD.Inventor: Kengo Omori
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Patent number: 12218592Abstract: A main comparator compares a feedback voltage VFB corresponding to an output voltage VOUT of a DC/DC converter with a reference voltage VREF and asserts a turn-on signal when the feedback voltage VFB falls below the reference voltage VREF. A timer circuit generates a turn-off signal S2 that transitions in level after an ON time TON proportional to (VOUT?VIN/VOUT has elapsed from assertion of the turn-on signal.Type: GrantFiled: August 26, 2022Date of Patent: February 4, 2025Assignee: ROHM CO., LTDInventors: Akihiro Kawano, Hiroaki Ando
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Patent number: 12218124Abstract: Disclosed is a gate control circuit that generates a gate control signal of an output transistor connected between an application end of a power supply voltage and an application end of an output voltage. The gate control circuit includes a first current source connected between the application end of the power supply voltage and the application end of the output voltage, a second current source connected between an application end of a booster voltage and an application end of a reference voltage, the booster voltage being raised to a voltage value higher than the power supply voltage in a steady state, an output stage that uses at least one of the first and second current sources to generate a gate charge current for charging a gate of the output transistor, and a controller that uses at least one of the first and second current sources according to the output voltage.Type: GrantFiled: October 26, 2022Date of Patent: February 4, 2025Assignee: ROHM Co., LTD.Inventors: Toru Takuma, Adrian Joita, Shuntaro Takahashi
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Publication number: 20250040207Abstract: A semiconductor device includes a semiconductor layer that is of a first conductivity type, a body region of a second conductivity type, a source region to be separated inwardly from an outer edge of the body region, a drain region formed on a surface of the semiconductor layer so as to be separated from the body region in a first direction orthogonal to a thickness direction of the semiconductor layer, a gate insulating layer formed on a portion of the surface of the semiconductor layer between the source region and the drain region in the first direction, a gate electrode that is formed on the gate insulating layer, an exposed region that is formed in the body region at a different position from the source region and in which the semiconductor layer is exposed, and a metal layer that forms a Schottky junction with the exposed region.Type: ApplicationFiled: October 17, 2024Publication date: January 30, 2025Applicant: ROHM CO., LTD.Inventor: Yusuke SHIMIZU
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Publication number: 20250040212Abstract: A nitride semiconductor device includes a nitride semiconductor layer including a first superlattice buffer layer, a second superlattice buffer layer formed above the first superlattice buffer layer, an electron transit layer formed above the second superlattice buffer layer and composed of a first nitride semiconductor, and an electron supply layer formed above the electron transit layer and composed of a second nitride semiconductor. The first superlattice buffer layer has a first superlattice structure including a first layer and a second layer alternately arranged. The first layer is composed of AlxGa1?xN, where 0<x<1. The second layer is composed of GaN. The second superlattice buffer layer has a second superlattice structure including a third layer and a fourth layer alternately arranged. The third layer is composed of AlyGa1?yN, where 0<y<x. The fourth layer is composed of GaN.Type: ApplicationFiled: July 15, 2024Publication date: January 30, 2025Applicant: ROHM CO., LTD.Inventor: Takuya KITO
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Publication number: 20250040211Abstract: An SiC semiconductor device includes an SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall, a source electrode embedded in the source trench and having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.Type: ApplicationFiled: October 16, 2024Publication date: January 30, 2025Applicant: ROHM CO., LTD.Inventors: Yuki NAKANO, Kenji YAMAMOTO, Seigo MORI
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Publication number: 20250040223Abstract: A semiconductor device according to the present invention is provided with a gate trench that is formed in a semiconductor layer, and a gate electrode that is embedded in the gate trench, with an insulating layer interposed therebetween. The gate trench includes a first outer peripheral gate trench section that is provided in an outer peripheral region thereof, and a second outer peripheral gate trench section that is provided outward of the first outer peripheral gate trench section. The semiconductor device is provided with, in the semiconductor layer, a first floating trench that is formed in a region between the first outer peripheral gate trench section and the second outer peripheral gate trench section, and a first floating electrode that is embedded in the first floating trench, with an insulating layer interposed therebetween, and that is in an electrically floating state.Type: ApplicationFiled: October 17, 2024Publication date: January 30, 2025Applicant: ROHM CO., LTD.Inventor: Masatsugu YUTANI
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Publication number: 20250040181Abstract: The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.Type: ApplicationFiled: October 7, 2024Publication date: January 30, 2025Applicant: ROHM CO., LTD.Inventor: Akihiro HIKASA
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Patent number: 12211817Abstract: A semiconductor device includes an insulating layer, conductors, a semiconductor element and a sealing resin. The insulating layer has first and second surfaces opposite to each other in the thickness direction. Each conductor has an embedded part whose portion is embedded in the insulating layer and a redistribution part disposed at the second surface and connected to the embedded part. The semiconductor element has electrodes provided near the first surface and connected the embedded parts of the conductors. The semiconductor element is in contact with the first surface. The sealing resin partially covers the semiconductor element and is in contact with the first surface. The redistribution parts include portions outside the semiconductor element as viewed in the thickness direction. The insulating layer has grooves recessed from the second surface in the thickness direction. The redistribution parts are in contact with the grooves.Type: GrantFiled: October 19, 2023Date of Patent: January 28, 2025Assignee: ROHM CO., LTD.Inventor: Kazunori Fuji