Abstract: A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer of a ridge shape with the gate electrode disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion from an upper end to a thickness direction intermediate portion of the gate electrode and a second etching step being a step differing in etching condition from the first etching step and being for forming remaining second portion of the gate electrode.

Abstract: A semiconductor device includes a semiconductor element, a mount portion, and a sintered metal bond. The semiconductor element includes a body and an electrode pad. The body has an obverse surface facing forward in a first direction and a reverse surface facing rearward in the first direction. The electrode pad covers the element reverse surface. The mount portion supports the semiconductor element. The sintered metal bond electrically bonds the electrode pad and the mount portion. The sintered metal bond includes a first rear edge and a first front edge spaced forward in the first direction from the first rear edge. The electrode pad includes a second rear edge and a second front edge spaced forward in the first direction from the second rear edge. The first front edge of the metal bond is spaced rearward in the first direction from the second front edge of the pad.

Abstract: A switching device includes: an N-type semiconductor substrate; a power MISFET having the N-type semiconductor substrate as its drain; an input electrode receiving an input signal; a control circuit generating a gate control signal for the power MISFET according to the input signal; and a negative current prevention circuit provided between the input electrode and the control circuit. The negative current prevention circuit includes: a P-channel MISFET connected, with its drain toward the input electrode and its source and back gate toward the control circuit, between the input electrode and the control circuit, with its gate fed with a fixed potential, with the potential at its back gate separated from the potential of the N-type semiconductor substrate; and a diode connected, with its anode toward the input electrode and its cathode toward the control circuit, between the input electrode and the control circuit.

Abstract: A linear power supply circuit includes: an error amplifier configured to output an error signal according to a difference between a feedback voltage based on an output voltage and a reference voltage; a first transistor configured to be controlled by the error signal; a current mirror circuit; a bias current source configured to distribute and supply a bias current to the first transistor and the current mirror circuit; a current amplifier configured to amplify a current outputted from the current mirror circuit; and a compensator configured to compensate for the bias current by a current corresponding to the current outputted from the current amplifier.

Abstract: A signal transmission device transmits a driving signal for a gate-driving transistor between a primary circuit system and a secondary circuit system while isolating between the primary and secondary circuit systems. The signal transmission device includes: a first external terminal configured such that the ground terminal of the secondary circuit system is connected to it; a second external terminal configured such that the terminal voltage at it varies according to whether the first external terminal is in an open state; and an open detection circuit configured to monitor the terminal voltage at the second external terminal to perform open detection for the first external terminal.

Abstract: A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

Abstract: There is provided a semiconductor device including: a lead frame including a first opening portion; a resin filled in the first opening portion; and a semiconductor element electrically connected to the lead frame, wherein a side wall surface of the lead frame in the first opening portion has a larger average surface roughness than an upper surface of the lead frame.

Abstract: A semiconductor power module including an insulating substrate having one surface and another surface, an output side terminal arranged at a one surface side of the insulating substrate, a first power supply terminal arranged at the one surface side of the insulating substrate, a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, and arranged at an other surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate, a first switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the first power supply terminal, and a second switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the second power supply terminal.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first surface electrode covering the diode region and the first conductivity type region on the first surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.

Abstract: A controller IC for a resonant switched capacitor converter includes a drive circuit and a frequency controller. The frequency controller controls a switching frequency based on an output voltage of the resonant switched capacitor converter.

Abstract: A semiconductor device includes a semiconductor chip having a main surface, a first conductivity type drift layer formed in a surface layer portion of the main surface, a trench gate structure formed in the main surface such as to be in contact with the drift layer, a second conductivity type channel region formed in the drift layer such as to cover a side wall of the trench gate structure, and first and second source/drain regions formed at intervals in a region along the side wall of the trench gate structure in the drift layer such as to oppose each other across the channel region.

Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.

Abstract: The present disclosure provides a main device, a sub-device and a communication system. The sub-device includes a receiver, a status signal transmitter, a read memory, and a status setting unit. The receiver is configured to receive a read command from the main device. The status signal transmitter is configured to transmit a status signal to the main device. The status setting unit is configured to determine whether a read data has been prepared in the read memory. When the read data has been prepared in the read memory, the status signal is set to a first state. When the read data has not been prepared in the read memory, the status signal is set to a second state.

Abstract: An isolated gate driver has: a register that stores the adjustment data read from a non-volatile memory; a gate driving circuit that drives the gate of a switching element with a characteristic set based on a value stored in the register; a fault detector that performs fault detection for other than the non-volatile memory; an error detection-correction circuit that performs error detection and error correction on the adjustment data written to the non-volatile memory; a first external terminal for output of the result of fault detection; a second external terminal for output of the result of error detection; and a fault controller that, if a one-bit error is detected in the adjustment data, brings the second external terminal into an error-indicating output state and continues with normal operation of the gate driving circuit and, if a two-or-more-bit error is detected in the adjustment data, forcibly stops the gate driving circuit.

Abstract: A terahertz element of an aspect of the present disclosure includes a semiconductor substrate, first and second conductive layers, and an active element. The first and second conductive layers are on the substrate and mutually insulated. The active element is on the substrate and electrically connected to the first and second conductive layers. The first conductive layer includes a first antenna part extending along a first direction, a first capacitor part offset from the active element in a second direction as viewed in a thickness direction of the substrate, and a first conductive part connected to the first capacitor part. The second direction is perpendicular to the thickness direction and first direction. The second conductive layer includes a second capacitor part, stacked over and insulated from the first capacitor part. The substrate includes a part exposed from the first and second capacitor parts.

Abstract: A linear regulator adjusts an intermediate voltage VREGOUT at an output node such that an output voltage VOUT at an output terminal approaches a first target voltage VOUT(REF1). A Dixon-type charge pump circuit enters a disable state when the output voltage VOUT is higher than a threshold voltage VTH(CP) determined to be lower than the first target voltage VOUT(REF1), outputs the intermediate voltage VREGOUT at a first input node to the output node in the disable state, enters an enable state when the output voltage VOUT is lower than the threshold voltage VTH(CP), and stabilizes the output voltage VOUT at the output terminal to a second target voltage VOUT(REF2) determined to be lower than the first target voltage VOUT(REF1) in the enable state.

Abstract: A non-volatile memory includes a memory cell having a first transistor and a second transistor, a driving circuit arranged to apply a read voltage to gates of the first and second transistors, and a signal output circuit arranged to output a signal associated with a first value or a signal associated with a second value, based on drain currents of the first and second transistors, in a read operation in which the read voltage is applied. The second transistor is constituted of a parallel circuit of a plurality of unit transistors, and gate width of each of the unit transistors is larger than that of the first transistor.

Abstract: A power supply system includes a plurality of semiconductor integrated circuit devices, wherein a master among the plurality of semiconductor integrated circuit devices is configured to use a constant voltage to calibrate a first reference of a detection result of a current flowing through its own switching element, and a slave among the plurality of semiconductor integrated circuit devices is configured to use the constant voltage supplied from the master to calibrate a second reference of a detection result of a current flowing through its own switching element.

Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

Abstract: A micro-electromechanical systems (MEMS) Z-axis accelerometer can comprise a substrate, a sensor configured to measure an acceleration along an axis that extends in a direction perpendicular to a plane of the substrate, and a spring axis configured to deform axially in response to the acceleration. The sensor can include a comb finger arrangement in which a comb finger overlap area is parallel with the spring axis. Fingers of the comb finger arrangement can extend in a non-sensing direction of lowest restoring force.