Abstract: This terahertz system includes: a transmitter that includes a first active element which oscillates a terahertz wave on the basis of the application of a first drive voltage, the transmitter being configured to be capable of transmitting the terahertz wave; a receiver that includes a second active element capable of detecting the terahertz wave on the basis of the application of a second drive voltage, and is configured to be able to receive the terahertz wave; and a control circuitry that outputs the first drive voltage and the second drive voltage. The control circuitry periodically and continuously changes the first drive voltage and the second drive voltage.

Abstract: A resistor includes a resistive element, a first electrode, and a second electrode. The first electrode is disposed at a gap from the second electrode. The first electrode and the second electrode each have a top surface and a bottom surface. The resistive element is arranged so as to span from the first electrode to the second electrode on the top surface side, and is welded to the first electrode and the second electrode. Weld junctions that are formed by welding the resistive element to the first electrode and the second electrode, respectively, are formed diagonally such that the width thereof in the direction in which the first electrode and the second electrode face each other decreases from the top surface to the bottom surface.

Abstract: A semiconductor device includes: a first chip mounted on a first die pad; a second chip mounted on a second die pad; an insulating chip mounted on the first die pad; a first bonding material for bonding the first die pad and the first chip; a second bonding material for bonding the second die pad and the second chip; and a third bonding material for bonding the first die pad and the insulating chip. The insulating chip includes: a third semiconductor substrate; a third insulating layer that is provided on the third semiconductor substrate; and a transformer that is disposed inside of the third insulating layer, and that includes a first coil and a second coil which are insulated from each other. The third semiconductor substrate is bonded to the first die pad by the third bonding material. The third bonding material is an insulating bonding material.

Abstract: This semiconductor device includes a plurality of sets of gate trenches, a plurality of gate electrodes, a plurality of field plate electrodes, a gate wiring, and a source wiring. The plurality of field plate electrodes each include two terminals connected to the source wiring. An outer peripheral gate wiring part of the gate wiring includes a gate finger that extends along a first direction in a plan view, and an inner gate wiring part includes a gate finger that extends along a second direction in a plan view. A first set of gate trenches extend along the first direction in a plan view and cross the gate finger, and a second set of gate trenches extend in the second direction in a plan view and cross the gate finger.

Abstract: The present disclosure is related to a transducer. The transducer includes a substrate. A plurality of vibrating membranes, in a configuration of cantilevers, are disposed on a main surface of the substrate. A plurality of piezoelectric elements are stacked on the plurality of vibrating membranes for generating a voltage to excite each vibrating membrane. The cantilevers of the plurality of vibrating membranes extend in a direction from a reference point on the main surface toward the cantilevers, or in a direction from the cantilevers toward the reference point.

Abstract: The present disclosure provides a thermal print head. The thermal print head includes: a heat resistor, a first electrode and a second electrode. The first electrode includes a base portion and an extension portion. The extension portion includes a first strip portion and a second strip portion. A first width of the first strip portion is less than a second width of the base portion at a conjunction between the second strip portion and the base portion. A third width of the second strip portion at the conjunction between the second strip portion and the base portion is less than the second width. A width of at least a portion of the second strip portion is equal to or less than the first width. A length of the second strip portion is greater than a half of a difference between a length of the first strip portion and a width of the heat resistor.

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a semiconductor layer formed on the principal surface of the semiconductor substrate, the semiconductor layer including a first-conductivity-type low concentration layer in contact with the principal surface of the semiconductor substrate and a first-conductivity-type high concentration layer that is formed at a surface layer portion of a surface, which is on a side opposite to the principal surface, of the semiconductor layer and that has a higher impurity concentration than the low concentration layer, and a Schottky electrode that is formed on the surface of the semiconductor layer and that forms a Schottky junction portion between the high concentration layer and the Schottky electrode.

Abstract: A nitride semiconductor device includes an electron transit layer, formed above a substrate, and an electron supply layer formed on the electron transit layer and having a larger band gap than the electron transit layer. A gate layer is formed on the electron supply layer and contains an acceptor impurity. A gate electrode is formed on the gate layer. A source electrode and a drain electrode are located at opposite sides of the gate layer and contact the electron supply layer. The gate electrode has a greater length than the gate layer in a first direction in which the source electrode, the gate layer, and the drain electrode are arranged. The gate electrode contacts an entire upper surface of the gate layer and extends from the gate layer toward at least one of the source electrode and the drain electrode.

Abstract: A semiconductor device manufacturing method includes a first preparation step, a second preparation step, a mounting step, a third preparation step, a placing step and a curing step. In the first preparation step, a first leadframe including an island part is prepared. In the second preparation step, a semiconductor element including an element obverse surface, an element reverse surface, a first electrode and a second electrode is prepared. In the mounting step, the semiconductor element is mounted on the island part with a first conductive paste interposed between the element reverse surface and the island part. In the third preparation step, a second leadframe including a first part, a second part, a frame part, a first connecting part and a second connecting part is prepared.

Abstract: In a switching power supply apparatus configured to generate an output voltage from an input voltage, the output voltage is obtained by rectifying and smoothing a switch voltage obtained by alternately turned on and off first and second transistors connected in series to each other in accordance with the output voltage. A light-load support circuit includes a reverse current detection circuit that outputs a reverse current detection signal when a magnitude of the switch voltage is lower than an offset voltage during an on period of the second transistor, and an offset correction circuit. In response to the reverse current detection signal, a transition to a specific state occurs, in which the first and second transistors are off. The offset correction circuit corrects the offset voltage on the basis of the switch voltage at a specific timing of being switched to the specific state.

Abstract: The present disclosure provides a switch device. The switch device includes a switch element, a DA converter and output voltage control unit. The switch element includes: a first end to which an input voltage is applicable; a second end to which an output voltage is applicable; and a control terminal. The output voltage control unit includes the switch element and configured to control the output voltage. The output voltage control unit is configured to generate a control voltage applicable to the control terminal such that the output voltage is gradually increased according to a ramp-like change in an output of the DA converter.

Abstract: A semiconductor device includes an n-type semiconductor layer, a p-type drift region formed in a surface layer portion of the semiconductor layer, an n-type body region formed in the surface layer portion of the semiconductor layer, a p-type drain region formed in a surface layer portion of the drift region, a p-type source region formed in a surface layer portion of the body region, a gate insulating film formed on a surface of the semiconductor layer, and a polysilicon gate formed on the gate insulating film, wherein a region extending from the source region to a side edge of the drift region is a channel region, and wherein the polysilicon gate includes a p-type first portion facing at least a portion of the channel region, and an n-type second portion facing at least a portion of the drift region.

Abstract: A power loss protection controller circuit for receiving an input voltage and supplying an output voltage to a load includes a bidirectional converter and a converter controller, wherein the bidirectional converter includes a bootstrap circuit, a high-side transistor, a low-side transistor, a high-side driver, a low-side driver, and a voltage maintenance circuit provided separately from the bootstrap circuit, and wherein the converter controller includes a feedback circuit, a logic circuit, and a high-side forced-on circuit.

Abstract: A semiconductor device includes a first conductive type semiconductor layer which has a principal surface, a second conductive type well region which demarcates an active region and an outer region on the principal surface and is formed on a surface layer portion of the principal surface and includes a high concentration portion high in impurity concentration on the active region side and includes a low concentration portion lower in impurity concentration than the high concentration portion on the outer region side, and a second conductive type impurity region of the active region which is formed on a surface layer portion of the principal surface.

Abstract: A semiconductor device includes a semiconductor substrate, an intermediate region including a stacked structure in which a first semiconductor region has stacked thereon a second semiconductor region, and a stacked structure in which a third semiconductor region has stacked thereon a fourth semiconductor region. The impurity concentration of the second semiconductor region is lower than those of the first semiconductor region and the third semiconductor region. The fourth semiconductor region and the third semiconductor region form a Zener diode. The third semiconductor region forms a PIN diode with the second semiconductor region, which is the uppermost layer of the intermediate region. The first semiconductor region and the second semiconductor region form a PIN diode. The first semiconductor region, which is the lowermost layer of the intermediate region, forms a Zener diode with the semiconductor substrate.

Abstract: An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer.

Abstract: A semiconductor device includes a first conductivity type first semiconductor region formed in a region on the first main surface side in a chip, a second conductivity type second semiconductor region formed in a region on the second main surface side in the chip, a first groove structure including a first groove formed in the first main surface while passing through the first semiconductor region so as to partition the first semiconductor region into a first region and a second region as viewed in cross-section, a control insulating film that covers a wall surface of the first groove, and a control electrode embedded in the first groove while sandwiching the control insulating film so as to control a channel in the second semiconductor region, a first electrode electrically connected to the first semiconductor region in the first region, and a second groove structure including a second groove formed in the first main surface while passing through the first semiconductor region in the second region, and a sec

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: A control circuit provided in a semiconductor device receives an input data signal during a selection period in which a selection signal has a predetermined level in synchronization with a clock signal and performs a corresponding operation corresponding to the input data signal during the selection period or after the selection period. The control circuit holds an error flag indicating whether a specific error has occurred, outputs, during a part of the selection period, a response signal corresponding to the input data signal from a data output terminal and outputs, during another part of the selection period, an error flag signal corresponding to the value of the error flag from the data output terminal.

Abstract: The present disclosure provides a switch device. The switch device includes: a switch element, including a gate, a drain, a source, a back gate, a first body diode disposed between the drain and the back gate and a second body diode disposed between the source and the back gate; a first switch circuit, including a first switch connected between the back gate and an application end at ground potential; and a second switch circuit, including a second switch connected between the back gate and the source.