Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

Abstract: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.

Abstract: A semiconductor device includes an insulating substrate, a first and a second obverse-surface metal layers disposed on an obverse surface of the insulating substrate, a first and a second reverse-surface metal layers disposed on a reverse surface of the insulating substrate, a first conductive layer and a first semiconductor element disposed on the first obverse-surface metal layer, and a second conductive layer and a second semiconductor element disposed on the second obverse-surface metal layer. Each of the first conductive layer and the second conductive layer has an anisotropic coefficient of linear expansion and is arranged such that the direction in which the coefficient of linear expansion is relatively large is along a predetermined direction perpendicular to the thickness direction of the insulating substrate. The first and second reverse-surface metal layers are smaller than the first and second obverse-surface metal layers in dimension in the predetermined direction.

Abstract: An OTP readout circuit includes an OTP circuit having a first OTP cell in which data is programmable only once, and a readout-possible signal output unit configured to generate a readout-possible voltage for reading out the data and output the generated readout-possible voltage to the OTP circuit. The readout-possible voltage from the readout-possible signal output unit causes the OTP circuit to read out the data programmed into the first OTP cell.

Abstract: According to the present invention, a semiconductor device includes a first conductivity type SiC layer, an electrode that is selectively formed upon the SiC layer, and an insulator that is formed upon the SiC layer and that extends to a timing region that is set at an end part of the SiC layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film. The length (A) of the interval wherein the organic insulating layer contacts the SiC layer is 40 ?m or more, and the lateral direction distance (B) along the electrode lower insulating layer between the electrode and SiC layer is 40 ?m or more.

Abstract: A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including electrodes on a front surface side and a back surface side thereof; and a graphite plate having an anisotropic thermal conductivity, the graphite plate of which one end is connected to the front surface side of the semiconductor device and the other end is connected to the insulating substrate, wherein heat of the front surface side of the semiconductor device is transferred to the insulating substrate through the graphite plate. There is provide an inexpensive power module capable of reducing a stress and capable of exhibiting cooling performance not inferior to that of the double-sided cooling structures.

Abstract: This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

Abstract: The present disclosure provides an optical element device. The optical element device includes: a semiconductor substrate, having a light receiving portion; a coating layer, covering the light receiving portion; and a transparent sealing resin, sealing the semiconductor substrate and the coating layer. The coating layer has a first coating layer surface facing the semiconductor substrate and a second coating layer surface located opposite to the first coating layer surface. The coating layer has a recess formed on the second coating layer surface. The transparent sealing resin contacts at least a portion of an inner peripheral surface of the recess.

Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.

Abstract: A video input interface receives video data. An OSD circuit draws an on screen display (OSD) character on the video data. The visibility detector checks whether the visibility of the OSD character is good or poor. A determination criterion for the visibility dynamically changes in a manner that depends on a background of the OSD character.

Abstract: Semiconductor device A1 of the present disclosure includes: semiconductor element 10 (semiconductor elements 10A and 10B) having element obverse face and element reverse face facing toward opposite sides in z direction; support substrate 20 supporting semiconductor element 10; conductive block 60 (first block 61 and second block 62) bonded to element obverse face via first conductive bonding material (block bonding materials 610 and 620); and metal member (lead member 40 and input terminal 32) electrically connected to semiconductor element 10 via conductive block 60. Conductive block 60 has a thermal expansion coefficient smaller than that of metal member. Conductive block 60 and metal member are bonded to each other by a weld portion (weld portions M4 and M2) at which a portion of conductive block 60 and a portion of metal member are welded to each other. Thus, the thermal cycle resistance can be improved.

Abstract: A switching power supply device includes a first switch with a first terminal connectable to an application terminal for the input voltage and a second terminal connectable to the first terminal of an inductor; a second switch with a first terminal connectable to the first terminal of the inductor and a second terminal connectable to an application terminal for a voltage lower than the input voltage; a third switch with a first terminal connectable to the first terminal of the inductor and a second terminal connectable to the second terminal of the inductor; a detector; and a controller. The controller produces, after occurrence or a sign of occurrence of an overshoot in the output voltage is detected by the detector until settlement of the overshoot in the output voltage, a control state in which to keep the first and second switches off and the third switch on.

Abstract: A semiconductor laser device A1 comprises a semiconductor laser chip 2 and a stem 1. The stem 1 includes a base 11 and leads 3A, 3B, and 3C fixed to the base, and supports the semiconductor laser chip 2. The semiconductor laser device A1 further comprises a first metal layer 15 including a first layer 151 covering the base 11 and the leads 3A, 3B, and 3C, a second layer 152 interposed between the first layer 151 and each of the base 11 and the leads 3A, 3B, and 3C, and a third layer 153 interposed between the second layer 152 and each of the base 11 and the leads 3A, 3B, and 3C. Crystal grains in the second layer 152 are smaller than crystal grains in the third layer 153. Such a configuration can suppress corrosion.

Abstract: A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.

Abstract: There is provided a semiconductor device including: a chip including a main surface; and a first transistor formed in the chip, wherein the first transistor includes: a first drain region of a first conductive type that is formed on a surface layer portion of the main surface; a first source region of the first conductive type that is formed on the surface layer portion of the main surface at an interval from the first drain region and partitions a first channel region having a first channel length L1 in a region between the first source region and the first drain region; a first gate insulating film that covers the first channel region; and a first gate electrode that contains polysilicon and is formed on the first gate insulating film.

Abstract: The present disclosure provides a thermal print head. The thermal print head includes a substrate, having a main surface facing one side in a thickness direction; a resistor layer, including a plurality of heat generating portions arranged in a main scanning direction and supported by the substrate; and a wiring layer, forming a power path to the plurality of heat generating portions and supported by the substrate. The substrate includes a convex portion protruding from the main surface and extending along the main scanning direction. The convex portion includes: a flat first surface on which each of the plurality of heat generating portions is disposed; and a first curved convex surface connected to the first surface.

Abstract: The present disclosure provides an optical element device. The optical element device includes: a semiconductor substrate, having a light receiving unit or a light emitting unit; a transparent sealing resin, sealing the semiconductor substrate; and a convex portion, directly or indirectly connected to the semiconductor substrate. The convex portion is covered by the transparent sealing resin.

Abstract: A semiconductor device comprises: a first semiconductor chip including a first obverse surface and a first reverse surface spaced apart from each other in a thickness direction; a second semiconductor chip including a second obverse surface and a second reverse surface spaced apart from each other in the thickness direction, and electrically connected in series to the first semiconductor chip; and a conductive member including a first conductive plate electrically connected to the first semiconductor chip and the second semiconductor chip. At least one of the first semiconductor chip and the second semiconductor chip is an IGBT including a collector electrode, an emitter electrode, and a gate electrode. The first conductive plate is provided between the first semiconductor chip and the second semiconductor chip in the thickness direction.

Abstract: The present disclosure provides a nitride semiconductor element. The nitride semiconductor element includes a semiconductor substrate having a substrate upper surface and a substrate lower surface facing opposite to the substrate upper surface, and having an active region and a peripheral region. A nitride semiconductor layer is selectively formed in the active region at the substrate upper surface to form a transistor. A source electrode and a drain electrode are in contact with the nitride semiconductor layer. A gate electrode is disposed between the source electrode and the drain electrode. A first electrode is formed on the substrate lower surface and used to electrically connect to the source electrode. The nitride semiconductor element includes a bidirectional Zener diode formed in the peripheral region and electrically connected to the first electrode.