Abstract: A semiconductor device includes: a well region formed in a surface region of a first main surface in a peripheral region, the well region separating the peripheral region located in a peripheral edge portion of the first main surface of a chip from an IGBT region; field regions of a first conductivity type separated from the well region toward a peripheral edge of the chip, the field regions being spaced apart from each other; and a cathode region of a second conductivity type formed in a surface region of a second main surface in the peripheral region, the cathode region forming a diode together with the well region. The cathode region is located closer to the peripheral edge of the chip than the well region is, and the cathode region is formed to face at least one of the field regions in a thickness direction of the chip.

Abstract: A nitride semiconductor device includes an electron transit layer composed of a nitride semiconductor, an electron supply layer formed on the electron transit layer and composed of a nitride semiconductor having a larger band gap than the electron transit layer, an insulation layer formed on the electron supply layer, and a specified electrode including a contact that contacts the electron supply layer through an opening extending through the insulation layer. The contact includes a conductive layer that contacts the electron supply layer. The conductive layer includes a contact layer containing at least one selected from titanium and tantalum and contacting and covering a portion of the electron supply layer exposed through the opening, and a diffusion layer containing a diffused metal and formed on the contact layer. The diffused metal is a metal contained in the electron supply layer.

Abstract: This semiconductor device includes a plurality of sets of gate trenches, a plurality of gate electrodes, a plurality of field plate electrodes, a gate wiring, and a source wiring. The plurality of field plate electrodes each include two terminals connected to the source wiring. An outer peripheral gate wiring part of the gate wiring includes a gate finger that extends along a first direction in a plan view, and an inner gate wiring part includes a gate finger that extends along a second direction in a plan view. A first set of gate trenches extend along the first direction in a plan view and cross the gate finger, and a second set of gate trenches extend in the second direction in a plan view and cross the gate finger.

Abstract: A semiconductor device includes a semiconductor chip that has a main surface, and a field insulating film that partially covers the main surface and has an insulating side wall in which an inclined angle made with the main surface is not less than 20° and not more than 40°.

Abstract: A semiconductor assembly may include a first layer, a second layer, a first material, and a second material. The first layer may be configured to transfer heat and second layer may be configured to dissipate at least a portion of the heat. The first material may include liquid metal droplets and a polymer, and may be disposed in contact with the first layer and the second layer. The first material may be configured to decrease at least one of a contact resistance or thermal resistance between the first layer and the second layer. The second material may be disposed in proximity to the first material, and may be configured to at least partially encapsulate the first material enhancing a stability of the first material and preventing exudation of at least one of the liquid metal droplets or the polymer from the first material based on one or more conditions.

Abstract: A semiconductor device includes a chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, and a terminal region of a second conductivity type formed in a surface layer portion of the semiconductor region at an interval in a thickness direction of the chip from the main surface in a peripheral edge portion of the main surface.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: A semiconductor device includes a substrate, a lower insulating film that is formed on the substrate, a resistor that is formed on the lower insulating film, and an upper insulating film that is formed on the lower insulating film such as to cover the resistor. The lower insulating film includes a first nitride film and a first SiO-based insulating film that is formed on the first nitride film and the upper insulating film includes a second nitride film. The resistor is formed on the first SiO-based insulating film and a lower surface of a peripheral edge portion of the second nitride film is joined to an upper surface of the first nitride film.

Abstract: A semiconductor device includes a plurality of terminals arranged along a first direction, a semiconductor element electrically connected to at least one of the plurality of terminals, and a sealing resin covering a part of each of the plurality of terminals and covering the semiconductor element. Each of the plurality of terminals includes a mount surface exposed from the sealing resin, and a side surface. The plurality of terminals include a first terminal located closest to one end in the first direction of the sealing resin and a second terminal spaced apart from the first terminal. The dimension in the thickness direction of the side surface of the second terminal differs from the dimension in the thickness of the side surface of the first terminal.

Abstract: A nitride semiconductor device includes an electron transit layer composed of a nitride semiconductor, an electron supply layer formed on the electron transit layer and composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer, a gate layer formed on the electron supply layer and composed of a nitride semiconductor including an acceptor impurity, a gate electrode formed on the gate layer, and a source electrode and a drain electrode that are formed on the electron supply layer. The gate layer includes an upper surface in contact with the gate electrode. The upper surface is a Ga-polar surface.

Abstract: An SSH circuit includes a plurality of unit lattices, each unit lattice including unit circuits. Each unit circuit includes two first inductors, a second inductor connected in series between the two first inductors, and two capacitors connected between a ground potential and two respective connection nodes at which the first and second inductors are connected to each other, an inductance of the second inductor being larger than that of the first inductors. In each unit lattice, the two connection nodes of each unit circuit are arranged at respective vertexes of both ends of each side forming a hyperrectangle, and the connection nodes arranged at each vertex being connected to each other and sharing the corresponding capacitor. The unit lattices are connected to each other by a mutual sharing of the first inductors by two unit lattices adjacent to each other. A peripheral edge has an uneven shape of unit lattices.

Abstract: Provided is a sensor module including a box-shaped structure that includes a bottom surface portion and a side surface portion arranged upright with respect to the bottom surface portion, a sensor unit that is mounted on the bottom surface portion of the box-shaped structure and that includes a pressure sensor body, and a cover member that is placed on the side surface portion in such a manner as to cover the sensor unit, in which an opening for allowing communication between a space inside the box-shaped structure housing the sensor unit and outside is formed on the side surface portion in the box-shaped structure.

Abstract: A plurality of yttria-stabilized zirconia sensors, a drive device, and a controller are provided. The drive device drives each of the plurality of sensors. The controller the controller sequentially switches between/among the plurality of sensors based on a prescribed condition.

Abstract: A semiconductor device includes a support member, semiconductor element, buffer layer and conductive member. The semiconductor element includes first and gate electrodes opposite from the side facing the support member in first direction. The semiconductor element is bonded to the support member. The buffer layer is electrically bonded to the first electrode. The conductive member is electrically bonded to the buffer layer. A first solid phase diffusion binding layer is between the first electrode and the buffer layer. The semiconductor element includes, on the same side as the gate electrode in first direction, a gate finger connected to the gate electrode. The gate finger includes a protrusion beyond the first electrode toward the buffer layer. The buffer layer includes a recess recessed from the side facing the semiconductor element in first direction. At least a part of the protrusion is accommodated in the recess.

Abstract: A semiconductor device includes a chip that has a first main surface on one side and a second main surface on another side, a pn-junction portion that is formed in an interior of the chip such as to extend along the first main surface, a device region that is provided in the first main surface, a first trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in the first main surface, and a second trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in a region further to the device region side than the first trench structure.

Abstract: A method of evaluating a natural frequency of a piezoelectric vibrator including a vibrating membrane and a piezoelectric element, includes: acquiring power-generating wave information of the piezoelectric vibrator from vibration of the vibrating membrane, which is caused by generating an electric field in a piezoelectric film of the piezoelectric element to displace the vibrating membrane and then extinguishing the electric field in a state where the vibrating membrane is displaced; and measuring a period of a power-generating wave based on the power-generating wave information and determining a reciprocal of the period as the natural frequency of the piezoelectric vibrator.

Abstract: In the semiconductor device, when bridge select data contained in received data indicates on status of through output of bit data, i.e. output of bit data as it is intact, between a first bus and a second bus, first device-dedicated data contained in the received data is through-outputted to the second bus, and moreover, when the bridge select data indicates on status of the through output and when communication by a specified second serial communication method dedicated to the first device has been set to the semiconductor device, a clock signal synchronized with the through-outputted data as well as a chip select signal are outputted.

Abstract: A semiconductor light emitting device includes a board including a first principal surface facing a first side in a thickness direction thereof, a first electrode provided on the board, a semiconductor light emitting element, and a light-transmitting resin that covers the element. The first electrode includes a first bonding portion and first, second, and third portions. The first bonding portion is formed on the first principal surface and is joined and electrically connected to the element. The first and second portions are each formed on the first principal surface and disposed on a first side in a first direction. The first portion is connected to the first bonding portion. The second portion is apart from the first bonding portion, and from the first portion in a second direction. The third portion is formed on a place different from the first principal surface, electrically connecting the first and second portions to each other.

Abstract: A semiconductor device includes: a substrate having an obverse surface; a first wiring layer on the obverse surface; a second wiring layer on the obverse surface, separated from the first wiring layer; a first semiconductor element having mutually opposite first obverse electrode and first reverse electrode, with the first reverse electrode bonded to the first wiring layer; a second semiconductor element having mutually opposite second obverse electrode and second reverse electrode, with the second reverse electrode bonded to the second wiring layer; and a conductive member separated from the substrate and bonded to the first and the second obverse electrodes. The first obverse electrode and the second obverse electrode have different polarities. The substrate includes an exposed portion between the first wiring layer and the second wiring layer. The conductive member overlaps with the exposed portion as viewed in the thickness direction of the substrate.

Abstract: A semiconductor device includes a conductive support member, a control element, an insulating element, a driver element and a sealing resin. The conductive support member includes a first lead and a second lead. The first lead has a first pad portion. The second lead has a second pad portion. The second pad portion is adjacent to the first pad portion in a first direction perpendicular to a thickness direction of the first pad portion. The control element is mounted on the first pad portion. The insulating element is mounted on the first pad portion and electrically connected to the control element. The driver element is mounted on the second pad portion and electrically connected to the insulating element. The sealing resin covers the first pad portion, the second pad portion, the control element, the insulating element and the driver element.