Abstract: A video transmission system includes an encoder, which includes a first transmission part that transmits a specific signal for communication establishment to a decoder via a first communication line during a blanking period of video data, and a determination part that determines communication establishment of back channel communication in a case of receiving a command signal indicating communication establishment from the decoder via a second communication line after transmission of the specific signal. The decoder includes a judgment part that judges whether or not a signal received from the encoder during the blanking period is the specific signal; and a second transmission part that transmits the command signal to the encoder via the second communication line in a case of the received signal being the specific signal, and the encoder and the decoder execute the back channel communication via the second communication line after determination of the communication establishment.

Abstract: A semiconductor device includes a conductor, a semiconductor element, and a sealing resin. The conductor has an obverse surface facing in the thickness direction. The semiconductor element includes an element body and a plurality of electrodes connected to the element body and bonded to the obverse surface. The sealing resin covers the semiconductor element. The sealing resin has a top surface facing the same side as the obverse surface in the thickness direction, and an opening penetrating the top surface in the thickness direction. The element body is exposed through the opening.

Abstract: A semiconductor device includes first and second semiconductor elements, and first and second circuits at different potentials. The second semiconductor element, electrically connected to the first semiconductor element, relays mutual signals between the first and the second circuits, while insulating them. The semiconductor device further includes a first terminal lead electrically connected to the first semiconductor element, a first wire connected to the first and the second semiconductor elements, and a second wire connected to the first semiconductor element and the first terminal lead. The first wire contains a first metal. The second wire includes a first core containing a second metal, and a first surface layer containing a third metal and covering the first core. The second metal has a smaller atomic number than that of the first metal. The third metal has a greater bonding strength with respect to the first terminal lead than the second metal.

Abstract: A pulse drive circuit includes: a buffer configured to receive a transmission pulse signal; a capacitor configured to be provided between the output terminal of the buffer and the primary coil of a transformer; and a first diode configured to be provided between the primary coil of the transformer and a reference potential terminal.

Abstract: A semiconductor device includes: an electroconductive support including leads; a first semiconductor element supported by the support; a second semiconductor element supported by the support; a third semiconductor element supported by the support, electrically connected to the first and the second semiconductor elements, and insulating the first and the second semiconductor elements from each other; and a sealing resin covering the first, the second and the third semiconductor elements and a part of the support. The support includes: a first part overlapping with the first semiconductor element as viewed in a thickness direction of the leads; a second part overlapping with the second semiconductor element as viewed in the thickness direction; and a third part overlapping with the third semiconductor element as viewed in the thickness direction. The third part is made of a non-magnetic material having a relative permeability of less than 100.

Abstract: The present disclosure provides a drive device. The drive device includes a burst generating circuit and a drive circuit. The burst generating circuit is configured to generate a burst signal. The drive circuit is configured to generate a pulse drive signal based on the burst signal and supply the pulse drive signal to a target-driving element. The pulse drive signal includes a first signal having a self-wave identification frequency and a second signal having a frequency other than the self-wave identification frequency.

Abstract: A semiconductor device includes first and second circuits, and an insulator relaying signals between the first and second circuits. The first circuit includes a first pad and a first semiconductor mounted on the first pad. The second circuit includes a second pad and a second semiconductor mounted on the second pad. The insulator may be mounted on the first pad. The semiconductor device further includes wire bonded to the insulator and second semiconductor. The wire includes an upright, inclined and extended sections. The upright section rises from the insulator along a thickness direction of the first pad. The inclined section is inclined relative to the thickness direction, extending from the second semiconductor toward the insulator. The extended section is between the upright and the inclined sections. The inclination angle of the extended section to a plane perpendicular to the thickness direction is smaller than that of the inclined section.

Abstract: A light-emitting element drive device includes, for example, a current sense amplifier configured to generate a current detection signal corresponding to a difference between a sense voltage corresponding to an inductor current (and thus an output current) supplied to a light-emitting element and a predetermined current setting signal (e.g., an offset voltage corresponding to a set current), an error amplifier configured to generate an error signal such that a direct-current component of the current detection signal has a zero value, a comparator configured to generate a set signal by comparing the current detection signal with the error signal, and a driver configured to perform feedback control of the output current in accordance with the set signal.

Abstract: A gate driving device comprises: a gate driving unit that outputs power for switching between on and off of a semiconductor switching element; a speed control unit that controls at least one of a turn-on speed and a turn-off speed of the semiconductor switching element; and a speed switching unit that switches at least one of the turn-on speed and the turn-off speed in response to an instruction from the speed control unit. The speed switching unit includes: a plurality of impedance elements (gate resistors, for example); and switches that control power output from the gate driving unit and to pass through corresponding ones of the plurality of impedance elements. The speed control unit controls the switches on the basis of an output current flowing in the semiconductor switching element.

Abstract: A semiconductor device includes a chip that has a main surface, a pad region that is provided in the main surface, a first electrode that is arranged on the main surface in the pad region, and to which a first potential is to be applied, a side wall dielectric film that covers a side wall of the first electrode in the pad region, and a second electrode that is arranged on the main surface so as to form a capacitive coupling with the first electrode via the side wall dielectric film in the pad region, and to which a second potential different from the first potential is to be applied.

Abstract: A semiconductor device includes a first impurity region, a second impurity region, and a third impurity region that are formed in a chip, a trench that is formed in the chip, a trench insulating film that is formed on an inner surface of the trench, an embedded body with conductivity that is embedded in the trench, and an electric field relaxation layer that is formed at a bottom portion of the trench and the electric field relaxation layer includes a first layer that is formed separated to the second principal surface side from the bottom portion of the trench and has a first impurity concentration and a second layer that is formed between the first layer and the bottom portion of the trench and has a second impurity concentration higher than the first impurity concentration.

Abstract: A semiconductor device includes a semiconductor chip which has a main surface and a main transistor which includes a first system transistor and a second system transistor that are each formed in the main surface so as to be individually controlled, in which the first system transistor includes a first composite cell which is constituted of an ?-number (??2) of first unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a first trench structure including a first electrode embedded in a first trench formed in the main surface, and the second system transistor includes a second composite cell which is arranged so as to be adjacent to the first composite cell and constituted of a ?-number (??2) of second unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a second trench structure including a second electrode embedded in a second trench formed in the main surface.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Loge(L2/SD), the dispersion degree is not less than 2 and not more than 15.

Abstract: A semiconductor device includes a driving circuit arranged to be capable of supplying a drive signal in an ultrasonic band to a piezoelectric element, a damping circuit having a resistance load and an inductive load, and a control circuit arranged to be capable of controlling the driving circuit and performing a reverberation reduction operation after stopping the supply of the drive signal to the piezoelectric element. In the reverberation reduction operation, the control circuit controls the driving circuit to supply the piezoelectric element with a damping signal having a phase different from that of the drive signal, and then enables the damping circuit to connect to the piezoelectric element.

Abstract: A signal processing device includes a wave-transmission signal generator configured to generate a wave-transmission signal for wave transmission of a sound wave, a wave-reception signal output unit configured to output a wave-reception signal based on wave reception of a sound wave, and a reflected-wave detection unit configured to detect, based on the wave-reception signal, a reflected wave of the wave transmission that may be included in the wave reception. The wave-transmission signal includes a first signal having a first predetermined number of waves, and a second signal generated after the first signal and having a second predetermined number of waves, the second predetermined number being smaller than the first predetermined number.

Abstract: This semiconductor device includes: an n-type drift layer; a p-type base region; a trench extending in the depth direction so as to pass through the base region and reach the drift layer; an insulating film formed on an inner surface of the trench; a gate trench surrounding the insulating film; and a p-type column region provided on the drift layer at a position at the bottom of the trench. The drift layer includes: a first region having a first concentration peak; and a second region that is provided at a position deeper than the trench and corresponding to the column region, and has a second concentration peak lower than the first concentration peak.

Abstract: A light receiving element array includes a substrate and a laminated semiconductor structure that is formed on the substrate. The laminated semiconductor structure includes a light absorbing layer that is disposed above the substrate and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer. Inside the laminated semiconductor structure, there is formed, for each window layer, a first of second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer. Inside the light absorbing layer, there is formed a second of second conductivity type region that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.

Abstract: Disclosed herein is a universal serial bus Type-C port controller mountable in a sink compatible with universal serial bus power delivery, the sink mounted with the universal serial bus port controller including a receptacle including a power supply terminal, a capacitor, a limiting resistance connected between the power supply terminal and the capacitor, and a bypass circuit that is switchable between a bypass state and a non-bypass state, and bypasses the limiting resistance in the bypass state. The universal serial bus Type-C port controller includes a charge control unit that monitors a voltage of the power supply terminal, sets the bypass circuit in the non-bypass state when the voltage of the power supply terminal is lower than a predetermined threshold voltage, and sets the bypass circuit in the bypass state when the voltage of the power supply terminal is higher than the threshold voltage.

Abstract: A semiconductor device includes a chip having a principal surface, a first conductivity type drift region formed at a surface layer portion of the principal surface, a trench electrode type gate structure formed on the principal surface such as to be placed in the drift region, and a second conductivity type well region formed along a bottom wall of the gate structure in a region below the gate structure in the drift region, wherein the well region includes a plurality of first well regions each of which is a first well region having a first bottom portion having a first depth and which are formed at an interval of a first interval from each other in a depth direction of the gate structure, and the first well regions adjacent each other face each other in the depth direction of the gate structure across a portion of the drift region.

Abstract: A semiconductor device includes a chip having a main surface, an active region provided in the main surface, a pad region provided outside the active region in the main surface, a transistor structure of an insulated gate type formed in the main surface in the active region, a capacitor structure of a trench electrode type that is formed in the main surface in the pad region and forms capacitive coupling with the chip, and a pad electrode that is arranged on the main surface in the pad region and is electrically connected to the capacitor structure.