Patents Assigned to ROHM Co., Ltd.
  • Patent number: 11916069
    Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 11916112
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Yasuhiro Kawakami, Yuki Nakano, Masaya Ueno, Seiya Nakazawa, Sawa Haruyama, Yasunori Kutsuma
  • Patent number: 11914439
    Abstract: A synchronous reset signal is generated from an asynchronous reset signal. The synchronous reset signal is output from the final-stage FF among L FFs connected in a cascade arrangement. A first error determination signal is output from the final-stage FF among M FFs connected in a cascade arrangement. Among N FFs connected in a cascade arrangement, the initial-stage FF receives the first error determination signal, and the final-stage FF outputs a second error determination signal. Based on the three outputs, the presence or absence of a fault in the circuit is determined. L, M, and N fulfil M?2, L?M+1, and M+N?L+1.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 27, 2024
    Assignee: Rohm Co., Ltd.
    Inventors: Hiromitsu Kimura, Yuji Kurotsuchi
  • Patent number: 11914219
    Abstract: A position detection unit generates a position detection value PFB that indicates the position of a control target. A temperature detection unit generates a temperature detection value that indicates the temperature. A correction unit corrects the position detection value PFB. A controller generates a control instruction value SREF such that the position detection value PFB_CMP subjected to the correction matches a position instruction value PREF that indicates the target position of the control target. A driver unit applies a driving signal that corresponds to the control instruction value SREF to an actuator. The correction unit corrects the position detection value PFB such that the relation between the position detection value PFB and the actual position exhibits linearity that is uniform independent of the temperature.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Jun Maede, Akihito Saito, Yoshihiro Sekimoto
  • Patent number: 11916000
    Abstract: A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a top surface, a bottom surface, and a first side surface connected to the top surface and the bottom surface. The first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region, the plurality of first terminals being exposed to the third region. A surface roughness of each of the top surface, the bottom surface, the first region, and the second region is larger than a surface roughness of the third region.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Hiroaki Matsubara
  • Patent number: 11916034
    Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Shoji Takei, Yuji Koga
  • Publication number: 20240061010
    Abstract: An acceleration detecting portion that detects an acceleration in a predetermined direction and an offset detecting portion that detects an offset amount with respect to the acceleration detecting portion are included. The offset detecting portion includes a second semiconductor substrate with a second cavity formed in its interior, a second fixed structure including a second fixed electrode that is supported, in a state of floating with respect to the second cavity, by the second semiconductor substrate, a second movable structure including a second movable electrode that is supported, in a state of floating with respect to the second cavity, by the second semiconductor substrate, and a disabling structure that disables a function of the second movable electrode displacing with respect to the second fixed electrode.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 22, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Hiroki MIYABUCHI
  • Publication number: 20240059554
    Abstract: A MEMS module includes a MEMS element provided with a substrate in which a hollow portion is formed, the MEMS element including a movable portion of the substrate which covers the hollow portion and has a thickness that allows a shape of the movable portion to be deformable, a first gauge resistor arranged on the substrate such that at least a portion of the first gauge resistor overlaps with the hollow portion, and a second gauge resistor arranged on the substrate in a region surrounding the first gauge resistor without overlapping with the hollow portion, and an electronic component configured to correct detection information of the MEMS element by using a first electrical signal detected by the first gauge resistor and a second electrical signal detected by the second gauge resistor and calculate an amount of change in air pressure.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 22, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Toru HIGUCHI, Kosuke YAMASHIRO
  • Patent number: 11908868
    Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Katsuhisa Nagao, Noriaki Kawamoto
  • Patent number: 11908777
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has a mounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Mamoru Yamagami
  • Patent number: 11909321
    Abstract: There is provided a power supply controller including: a monitor voltage generation part configured to generate a monitor voltage according to a primary voltage of a transformer that forms an insulated switching power supply; a sample/hold part configured to sample/hold the monitor voltage and output a feedback voltage; and a controller configured to turn on/off a primary current of the transformer by a fixed on-time method according to the feedback voltage, wherein the sample/hold part samples/holds the primary voltage at a plurality of different timings and outputs one of a plurality of hold values as the feedback voltage.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 20, 2024
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshinori Sato, Yohei Akamatsu, Satoru Nate, Hiroaki Sawaoka
  • Patent number: 11907492
    Abstract: A control circuit controls an input apparatus to be used underwater. A sense pin is coupled to a sensor electrode arranged so as to allow the user wearing equipment to touch the sensor electrode. A capacitance sensor is coupled to the sense pin, and detects the electrostatic capacitance formed by the sensor electrode. When the electrostatic capacitance Cs detected by the capacitance sensor becomes lower than a predetermined threshold value, the processing unit judges that a touch input by the user has occurred.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Hirotoshi Usui
  • Patent number: 11909329
    Abstract: A semiconductor unit includes a semiconductor device, a controller, and a resistor. The semiconductor device includes a transistor arranged between a positive electrode of a battery and an inverter circuit electrically connected to the battery. The controller is connected to a control terminal of the transistor and configured to control the transistor. The resistor arranged between the control terminal and the controller. The controller controls the transistor so that when a current flowing to the transistor is greater than or equal to a threshold value, the transistor is deactivated. The resistor has a resistance value that is greater than or equal to 100 ?.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Mineo Miura, Masashi Hayashiguchi, Jun Terada
  • Patent number: 11908927
    Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 13 that constitutes an electron transit layer, a second nitride semiconductor layer 14 that is formed on the first nitride semiconductor layer and constitutes an electron supply layer, a nitride semiconductor gate layer 15 that is disposed on the second nitride semiconductor layer, has a ridge portion 15A at least at a portion thereof, and contains an acceptor type impurity, a gate electrode 4 that is disposed at least on the ridge portion of the nitride semiconductor gate layer, a source electrode 3 that is disposed on the second nitride semiconductor layer and has a source principal electrode portion 3A parallel to the ridge portion, and a drain electrode 5 that is disposed on the second nitride semiconductor layer and has a drain principal electrode portion 5A parallel to the ridge portion.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Shinya Takado, Kentaro Chikamatsu
  • Publication number: 20240055384
    Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 15, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Kazumasa TANIDA, Osamu MIYATA
  • Publication number: 20240055474
    Abstract: A semiconductor device includes: a semiconductor layer; cell trenches formed in the semiconductor layer; an insulating layer on the semiconductor layer; electrodes, each embedded in corresponding one of the cell trenches via the insulating layer; and one or more outer peripheral trenches formed in the semiconductor layer, wherein the cell trenches include: first set of cell trenches extending in first direction and arranged at first pitch in second direction; and second set of cell trenches extending in the second direction and arranged at second pitch in the first direction, wherein the semiconductor layer includes first and second cell regions where the first and second sets of cell trenches are arranged respectively, and the one or more peripheral trenches surround the first and second cell regions in a plan view, and wherein inter-cell distance between the first and second cell regions is smaller than both the first and second pitches.
    Type: Application
    Filed: July 19, 2023
    Publication date: February 15, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Akihiro SAITO, Kenta WATANABE
  • Publication number: 20240053377
    Abstract: An acceleration sensor includes a first substrate and a second substrate, wherein the first substrate includes: a first anchor region provided on a partial region of a bottom surface of a first substrate cavity; a first anchor protruding from the first anchor region toward the second substrate along a first direction; a spring extending from the first anchor in a second direction perpendicular to the first direction; and a movable electrode mechanically connected to and electrically insulated from the spring, and configured to be displaced in the first direction, and wherein the second substrate includes: a second anchor region provided on a partial region of a bottom surface of a second substrate cavity; a second anchor protruding from the second anchor region toward the first substrate along the first direction; and a fixed electrode mechanically fixed to the second anchor and facing the movable electrode.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 15, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Martin Wilfried HELLER
  • Patent number: 11901489
    Abstract: An electrode structure includes: an indium tin oxide (ITO) electrode that includes ITO; an Al electrode that includes Al and covers the ITO electrode; and a barrier electrode that includes at least one of TiN and Cr and is interposed in a region between the ITO electrode and the Al electrode.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: February 13, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Ryosuke Ishimaru, Yohei Ito, Yasuo Nakanishi
  • Patent number: D1015283
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yoshihisa Tsukamoto
  • Patent number: D1015284
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yoshihisa Tsukamoto