Abstract: A thermal printhead includes a plurality of heating resistor portions, a first capacitor, a switch section, and a first resistor. The heating resistor portions are electrically connected in parallel to each other. The first capacitor is electrically connected in parallel to the heating resistor portions. The switch section is electrically connected in series to the first capacitor. The first resistor is electrically connected in parallel to the first capacitor.

Abstract: A method of evaluating a natural frequency of a piezoelectric vibrator including a vibrating membrane and a piezoelectric element, includes: transmitting a drive signal to the piezoelectric element for a certain period of time so as to allow the vibrating membrane to vibrate; acquiring information about a power-generating wave of the piezoelectric vibrator after stopping the transmission of the drive signal to the piezoelectric element; and determining a frequency of the drive wave at which a value of a voltage of the power-generating wave is maximum as the natural frequency of the piezoelectric vibrator, based on the information about the power-generating wave.

Abstract: A signal generation circuit includes: a reference voltage generation circuit configured to generate a reference voltage; a ramp voltage generation circuit configured to generate a ramp voltage that varies within a predetermined voltage range; and a comparison circuit configured to output a comparison result signal that indicates the magnitude relationship between the reference voltage and the ramp voltage. The reference voltage generation circuit gives the reference voltage a waveform of a triangular wave and varies the frequency of the triangular wave.

Abstract: The stabilized voltage generation circuit includes: a first voltage generation circuit configured to generate a first voltage with positive temperature characteristics; and a second voltage generation circuit including a first MOSFET having a gate of a first conductivity type and a second MOSFET having a gate of a second conductivity type different from the first conductivity type and configured to generate a second voltage with negative temperature characteristics based on the difference in gate threshold voltage between the first and second MOSFETs. The output voltage is generated based on the sum voltage of the first and second voltages.

Abstract: A semiconductor device is provided with: a first switching element; a driver positioned so as to be displaced with respect to the first switching element in the z-direction, the driver driving the first switching element; a first resin layer for encapsulating the first switching element; and a first control via conductor extending through the first resin layer in the z-direction and electrically connecting the first switching element and the driver.

Abstract: In the switching power supply device, a controller has a first state in which it keeps a first switch on and a second switch off, a second state in which it keeps the first switch off and the second switch on, a third state in which it keeps the first and second switches off, and a fourth state in which it keeps a voltage at a connection node between the first and second switches lower than in the third state. The controller repeats the first, second, third, and fourth states on a basis of a periodic signal, and masks the periodic signal until detecting a zero-crossing point of a current flowing through an inductor.

Abstract: A control circuit configured to be capable of controlling a DC/DC converter includes: a switching controller configured to be capable of controlling an output circuit of the DC/DC converter in a continuous mode where the output circuit is continuously operated and a discontinuous mode where an idle period is set, wherein the switching controller includes: a first comparator configured to output a differential signal indicating a result of comparison between a voltage based on an output voltage and a first reference voltage; an operation signal output circuit configured to output an operation signal for starting an operation of the DC/DC converter when the differential signal exceeds a predetermined level; and a corrector configured to raise a level of the first reference voltage or lower the voltage based on the output voltage after receiving a forced continuous operation signal that switches from the discontinuous mode to the continuous mode.

Abstract: For example, the switching drive device 100 includes a driver 30 configured to drive an N-type semiconductor switch element, a current limiter 50 configured to limit a current fed to a boot capacitor BC1 included in a bootstrap circuit BTC, and a current controller 60 configured to control the operation of the current limiter 50. The current controller 60 is configured to drive the current limiter 50 to limit the current fed to the boot capacitor BC1 when the charge voltage across the boot capacitor BC1 is higher than a threshold value.

Abstract: This semiconductor device comprises a substrate, a first wiring part, a second wiring part, and a semiconductor element. The first wiring part includes a first through-electrode, first main-surface wiring, and a first wiring electrode. The second wiring section includes a second through-electrode, second main-surface wiring, and a second wiring electrode. An upper surface is depressed toward the interior of the first through-electrode. The first wiring electrode is joined to a first element electrode of the semiconductor element by a first joining member. The second wiring electrode is joined to a second element electrode of the semiconductor element by a second joining member. The first wiring electrode, which is formed on an upper surface of the first main-surface wiring, is larger than the second wiring electrode, which is formed on an upper surface of the second main-surface wiring, as seen from the thickness direction.

Abstract: A linear power supply includes: a first transistor configured to be connectable between an input terminal configured to input an input voltage thereto and an output terminal configured to output an output voltage therefrom; a reference voltage generator configured to generate a reference voltage; a controller configured to control the first transistor based on the difference between a feedback voltage reflecting the output voltage and the reference voltage; and a second transistor configured to be connectable between the input terminal or the output terminal and the first transistor and configured to clamp the first terminal-to-second terminal voltage of the first transistor.

Abstract: In an ion implantation processing system including an ion implantation device, the ion implantation device acquires, from a server, off-angle data of a wafer that is an ion implantation processing target and controls an ion implantation angle with respect to the wafer based on the off-angle data.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, a first high resistance unit embedded in the insulating layer and disposed so as to surround a first electrode in a plan view, a second high resistance unit embedded in the insulating layer and disposed so as to surround a second electrode in a plan view, and low resistance units for voltage detection that are electrically connected to the first high resistance unit and the second high resistance unit, and have lower resistances than the first high resistance unit and the second high resistance unit.

Abstract: Disclosed herein is a semiconductor light emitting device including a semiconductor light emitting element, a Zener diode, and a conductive support component that supports the semiconductor light emitting element and the Zener diode. The semiconductor light emitting element has a first electrode. The semiconductor light emitting device further includes a first wire connected to the Zener diode and the first electrode.

Abstract: A delay control circuit generates output timing signals that cause pixel drive signals to be output at timings after elapse of different delay times. The delay control circuit includes: first to sth delay timing signal generation circuits, generating first to kth delay timing signals that bring about output timings increasing in delay time; a control signal generation circuit, supplying a start pulse signal that initiates generation of the first to kth delay timing signals to the first to sth delay timing signal generation circuits; and a delay signal selection circuit, for each output channel with respect to first to sth delay timing signal groups each including the first to kth delay timing signals, selecting from among s delay timing signals the delay timing signal that brings about an earliest output timing, and setting the delay timing signals as the first to kth output timing signals.

Abstract: For example, a semiconductor device includes one or more first subcontacts electrically conducted to a substrate. At least one of the one or more first subcontacts is formed in an element arrangement region, and has a lower impedance than the substrate. Preferably, at least one of the one or more first subcontacts is adjacent to a circuit element formed in the element arrangement region. Preferably, on the substrate, which is of a first conductivity type, an epilayer of a second conductivity type is formed, and the one or more first subcontacts include a first line having a lower impedance than the substrate, and a semiconductor region of the first conductivity type penetrating through the epilayer to electrically conduct the first line and the substrate to each other.

Abstract: A driving circuit controls driving of a switching element by outputting a driving signal to the switching element. The driving circuit includes an air-core transformer having a plurality of primary windings and a secondary winding magnetically coupled to each of the plurality of primary windings. An AC signal is input to each of the plurality of primary windings of the air-core transformer. The plurality of primary windings includes a first primary winding and a second primary winding. There is a phase difference between an AC signal input to the first primary winding and an AC signal input the second primary winding.

Abstract: Provided is a light-emitting element drive system including a leader light-emitting element drive device configured to be capable of driving light-emitting elements, and to include a DC/DC controller configured to be capable of controlling an output stage that can output an output voltage; and a plurality of follower light-emitting element drive devices configured to be capable of driving the light-emitting elements applied with the output voltage. The follower light-emitting element drive device includes at least one signal output terminal capable of outputting an operation information signal related to driving of the light-emitting elements. A plurality of the signal output terminals are connected to the same node, and the same node is connected to a signal input terminal of the leader light-emitting element drive device.

Abstract: An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer.

Abstract: A semiconductor device includes a first conductive type semiconductor layer which has a principal surface, a second conductive type well region which demarcates an active region and an outer region on the principal surface and is formed on a surface layer portion of the principal surface and includes a high concentration portion high in impurity concentration on the active region side and includes a low concentration portion lower in impurity concentration than the high concentration portion on the outer region side, and a second conductive type impurity region of the active region which is formed on a surface layer portion of the principal surface.