Abstract: A transducer includes: a substrate including a main surface and a back surface facing the main surface; a plurality of vibrating films formed in the substrate at a predetermined thickness between the main surface and a plurality of recesses formed in the back surface of the substrate such that the main surface can vibrate in the thickness direction of the substrate; and a plurality of driving layers laminated on the plurality of vibrating films, each being constituted by a pair of electrode layers of a lower electrode layer and an upper electrode layer with a piezoelectric layer therebetween and being disposed on the main surface, in which the plurality of vibrating films include vibrating films arranged at predetermined intervals in each of at least two directions in a plane of the main surface, and the transducer generate sufficient sound volume because the transducer is used as a speaker.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulation layer arranged on the semiconductor substrate, a source pad formed on a head surface of the insulation layer and electrically connected to the source electrode, a drain pad formed on the head surface of the insulation layer and electrically connected to the drain electrode, a gate pad formed on the head surface of the insulation layer and connected to the gate electrode, a specified pad formed on the head surface of the insulation layer, and a capacitor. The capacitor includes a source-side electrode, electrically connected to the source electrode, and a specified electrode, electrically connected to the specified pad and arranged facing the source-side electrode.

Abstract: A method for processing a semiconductor wafer comprises: preparing a semiconductor wafer including a main body and a rim, the rim having a greater thickness than the main body and including a projection projecting; supporting the semiconductor wafer with a holding tape; preparing a base including a stage and an outer portion; setting the semiconductor wafer on the base so that the main body is supported by a support surface of the stage; and separating the main body and the rim by cutting an edge portion of the main body in a state in which the main body is supported by the stage. The setting the semiconductor wafer on the base includes setting the semiconductor wafer on the base so that the main body is supported by the stage in a state in which the projection is separated from a head surface of the outer portion of the base.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Loge (L2/SD), the dispersion degree is not less than 2 and not more than 15.

Abstract: The present disclosure provides a thermal print head and a method of fabricating the thermal print head. The thermal print head includes a substrate made of a semiconductor material and having a main surface and a convex portion, a resistor layer including a plurality of heat generating portions on the convex portion, and a wiring layer conducted to the plurality of heat generating portions and formed to contact the resistor layer. The convex portion has a top surface, a first inclined surface and a second inclined surface. At least one of two ends of the convex portion in the main scanning direction forms a third inclined surface connected to the main surface and the first inclined surface, and a fourth inclined surface connected to the main surface and the second inclined surface.

Abstract: A semiconductor device includes a semiconductor layer, a Schottky electrode that is formed at a first surface of the semiconductor layer and that forms a Schottky junction Sj between the semiconductor layer and the Schottky electrode, and the Schottky electrode has a first portion that is selectively formed near the first surface of the semiconductor layer in a thickness direction of the Schottky electrode and that is made of Ti containing oxygen. The Schottky electrode may have a second portion that is formed on the first portion and that is made of Ti and N.

Abstract: A support stage includes a base portion, a support portion that is erected at a peripheral edge portion of the base portion and with which one surface of a wafer is to be come into contact, a suction groove that is provided at the support portion and to which a suction force with respect to the one surface is to be given, an ejecting hole that is provided in an inward portion of the base portion and by which a gas is to be ejected toward the one surface, and an exhaust hole that is provided in at least either one of the base portion and the support portion and by which a gas is to be discharged from a space between the base portion, the support portion, and the one surface.

Abstract: A DCO is configured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that corresponds to a control code, and such that, during a period in which the selection signal SEL is negated, an injection edge based on a reference clock can be injected. During the startup period of a PLL circuit, a controller repeats a cycle including (i) a process in which the selection signal is asserted so as to oscillate the DCO, and phase comparison is made between an oscillator clock and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the DCO, and the control code is updated by a binary search based on a result of the phase comparison.

Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.

Abstract: A non-volatile storage device includes a memory that stores data in a non-volatile manner, a power supply that generates an internal voltage to feed it to the memory, a controller that controls the memory and the power supply, an A/D converter that performs A/D conversion on the internal voltage, and a fault detector that detects a fault related to data written in the memory based on the output of the A/D converter.

Abstract: A lamp control device comprises a first input terminal, a second input terminal, an output terminal that is configured to be connectable to a lamp via an external switch and outputs a drive current for the lamp, an internal switch provided on a first path connecting the first input terminal and the output terminal, a constant current section provided on a second path connecting the second input terminal and the output terminal, a voltage monitoring section that monitors a voltage applied to the output terminal, and a control section that controls the internal switch on the basis of a monitoring result from the voltage monitoring section.

Abstract: A semiconductor device includes a conductive support member, a first semiconductor element, and a second semiconductor element. The conductive support member includes a first die pad and a second die pad separated from each other in a first direction. The first die pad and the second die pad overlap each other when viewed along the first direction. The first die pad has a first main surface mounting the first semiconductor element, and a first back surface opposing the first main surface. The second die pad has a second main surface mounting the second semiconductor element, and a second back surface opposing the second main surface. When viewed along a second direction, a distance in the first direction between the first back surface and the second back surface is larger than a distance in the first direction between the first main surface and the second main surface.

Abstract: In a first light emission control device, a clock signal is generated, and after a first driving sequence starts to be performed in which the respective states of light-emitting elements in a first light-emitting element array are sequentially switched synchronously with the clock signal, at a particular time point a characteristic of the clock signal is changed from a first characteristic to a second characteristic. After the change, in a second light emission control device, a second driving sequence is performed in which the respective states of light-emitting elements in a second light-emitting element array are sequentially switched synchronously with the clock signal.

Abstract: A liquid crystal display device includes a pixel array including a plurality of rows of gate lines, a plurality of columns of source lines, a plurality of switches, and a plurality of liquid crystal cells; a gate driver IC connected to the gate lines; a source driver IC connected to the source lines; a timing control IC arranged to control operation timings of the gate driver IC and the source driver IC; and a system power supply IC arranged to supply a power supply voltage to the source driver IC. Each of the timing control IC and the system power supply IC has a function of detecting an abnormality in the gate driver IC and an abnormality in the source driver IC.

Abstract: For example, the switching drive device 100 includes a driver 30 configured to drive an N-type semiconductor switch element, a current limiter 50 configured to limit a current fed to a boot capacitor BC1 included in a bootstrap circuit BTC, and a current controller 60 configured to control the operation of the current limiter 50. The current controller 60 is configured to drive the current limiter 50 to limit the current fed to the boot capacitor BC1 when the charge voltage across the boot capacitor BC1 is higher than a threshold value.

Abstract: A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction.

Abstract: A switch device includes an output transistor, an overcurrent protection circuit configured to be capable of performing an overcurrent protection operation in which magnitude of target current flowing in the output transistor is limited to a predetermined upper limit current value or less, and a control circuit configured to be capable of controlling a state of the output transistor and capable of changing the upper limit current value among a plurality of current values including a predetermined first current value and a predetermined second current value less than the first current value. The control circuit can limit the magnitude of the target current to the first current value or less in response to the magnitude of the target current reaching the first current value, and then change the upper limit current value to the second current value.

Abstract: A semiconductor device includes an interlayer insulating film, and a wiring of an uppermost layer arranged on the interlayer insulating film, wherein the wiring includes a seed layer arranged on the interlayer insulating film and a wiring body portion arranged on the seed layer, wherein a constituent material of the wiring body portion is copper or a copper alloy, and wherein a trench is formed in an upper surface of the interlayer insulating film along an outer edge of the interlayer insulating film in a plan view.

Abstract: An SiC semiconductor device includes an SiC semiconductor chip that has a main surface, an n-type drift region that is formed in a surface layer portion of the main surface and has an impurity concentration adjusted by at least two types of pentavalent elements, and a p-type impurity region that is formed inside the drift region such as to form a pn-junction portion with the drift region.