Abstract: A method for sensing logical content stored in a memory cell, the method including inputting an input cell current of a selected array cell of a memory array to an input stage, and folding the input cell current and using it to discharge an input of a latch, the latch providing an output digital signal indicative of a logical content stored in the selected array cell.

Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with a group of memory cells of a non-volatile memory cell array, allowing correct reading of the group of history cells, selecting a memory read reference level according to the first read reference level, and reading the non-volatile memory array cells.

Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Abstract: A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.

Abstract: A method for creating a non-volatile memory array includes generating polysilicon columns on top of an oxide-nitride-oxide (ONO) layer, creating spacing elements on the sides of the polysilicon columns, implanting bit lines into the substrate at least between the spacing elements, depositing oxide filler over the bit lines, depositing a second polysilicon layer over the array and etching the second polysilicon layer into word lines and the polysilicon columns between the word lines.

Abstract: A method for embedding non-volatile memories with logic circuitry, without changing performance of both the logic circuitry and the NVM elements (and/or without changing a sequence of manufacturing steps for both the logic circuitry and the NVM elements). The embedding process includes insertion of NVM device and array process steps into an existing logic CMOS process in a way that maintains the CMOS performance, thereby enabling use of existing circuit libraries. The NVM may thus be combined with the high-speed low-voltage CMOS without any performance or reliability penalty.

Abstract: The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure.

Abstract: The present invention is a method, circuit and system for determining a reference voltage to be used in reading cells programmed to a given program state. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in a NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read and the number of cells found at a given state associated with the array may be compared to one or more check sum values obtained during programming of the at least a subset of cells. A Read Verify threshold reference voltage associated with the given program state or associated with an adjacent state may be adjusted based on the result of the comparison.

Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

Abstract: A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor T1 and an NMOS transistor T2, the PMOS transistors T1 sharing a common deep N well and the NMOS transistors T2 connected to a P well, wherein during negative charging, the NMOS transistors T2 shunt leakage current to ground, and during positive charging, the PMOS transistors T1 shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.

Abstract: Apparatus including a virtual ground array, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. The virtual ground array includes at least one block of data, and peripheral circuitry adapted to simultaneously access a plurality of subsets of the at least one block of data stored in the memory cells along at least one word line. Methods for operating the virtual ground array in a mass storage device include simultaneously accessing a plurality of subsets of at least one block of data stored in the memory cells along at least one word line.

Abstract: A method for operating on bits of a memory cell, the method comprising providing a memory cell that has two separated and separately chargeable areas on first and second sides of the cell, each chargeable area defining one bit, applying an injection pulse and a verify pulse on the first side of the cell, and before the first side of the cell has reached a verify level, applying an injection pulse and a verify pulse on the second side of the cell.

Abstract: A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.

Abstract: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving the same sensing accuracy with improved read disturb immunity.

Abstract: A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit.

Abstract: A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit.

Abstract: A method for operating a memory device, the method comprising marking a portion of a memory device associated with a group of bits comprising at least one bit upon which an operation is to be performed, and operating on the group of bits and skipping operating on at least one unmarked portion of the memory device in an operation cycle of the memory device. A random access memory (RAM) device is also disclosed comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of the addresses in the RAM device.

Abstract: Circuitry including a voltage regulator including a first stage and a second stage, wherein an output of the first stage is coupled to an input of the second stage, wherein current of the second stage is mirrored through a current path to a current mirror driver, the current mirror driver adapted to perform a first Class AB action including at least one of sourcing and sinking current from a voltage supply VPP, wherein an output of the current mirror driver is connected to an output of the voltage regulator, and a first circuit connected to the current path and adapted to sample current in the current path, wherein during steady state current in the current path, the first circuit provides negligible current to the output of the voltage regulator, and during transient current conditions, the first circuit performs a second Class AB action complementary to the first Class AB action including at least one of sinking and sourcing current from the voltage supply VPP.

Abstract: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.