Abstract: A discharge device comprising a transistor configured as a source follower, a capacitance load to be discharged connected via a switch to a source terminal of the source follower, a reference voltage connected to a gate terminal of the source follower, and a current load element connected to a drain terminal of the source follower.

Abstract: A method for erasing a bit of a memory cell in a non-volatile memory cell array, the method comprising applying an erase pulse to at least one bit of at least one memory cell of the array, waiting a delay period wherein a threshold voltage of the at least one memory cell drifts to a different magnitude than at the start of the delay period, and after the delay period, erase verifying the at least one bit to determine if the at least one bit is less than a reference voltage level.

Abstract: A NOR array includes a first plurality of word lines, a second plurality of bit lines and a third plurality of common lines. Each word line connects to the gates of a row of nitride read only memory (NROM) cells. Each bit line connects to one diffusion area of each NROM cell in a column of the NROM cells and each common line connects to the other diffusion areas of each NROM cell in a row of the NROM cells.

Abstract: An operational amplifier comprising an inverting stage transistor that drives current to an output of the operational amplifier through a current path, and an auxiliary transistor that adds transient current to the current path and which remains dormant under steady-state conditions.

Abstract: A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Abstract: According to some embodiments of the present invention, a non-volatile memory cell may be operated using a charge pump circuit. The charge pump circuit may be adapted to output a first and second voltage level, and the charge pump circuit may be connected to a first circuit segment, including a select transistor associated with the memory cell, through a switch. When the charge pump circuit is outputting power at the first voltage level, the switch may be conducting and the select transistor line may be charged. When the charge pump circuit is outputting power at the second voltage level, the switch may be opened and a second circuit segment, including a bit line associated with the memory cell, may be charged.

Abstract: A method for protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light. A device constructed in accordance with the method is also disclosed.

Abstract: A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Abstract: A flash memory card including a controller, at least one control pad, at least one memory, and a high voltage switch logic module in communication with the at least one control pad, the controller and the at least one memory, the high voltage switch logic module being adapted to selectively route voltage from the at least one control pad to one of the controller and the at least one memory. If the voltage input to the at least one control pad does not exceed a predefined level, then the voltage may be routed from the at least one control pad to the controller. If the voltage input to the at least one control pad exceeds the predefined level, then the voltage may be routed from the at least one control pad to the at least one memory.

Abstract: A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the nitride layer. Another method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a portion of a top oxide layer, thereby causing oxygen to be introduced into the nitride layer and depositing a remaining portion of the top oxide layer, thereby assisting in controlling the amount of oxygen introduced into the nitride layer. A farther method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby causing oxygen to be introduced into the nitride layer.

Abstract: An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded.

Abstract: A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control tern connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

Abstract: A virtual ground array includes memory elements, select transistors, select lines connected with the select transistors, word lines, global bit lines and local bit lines connecting the select transistors with the memory elements, wherein each of the memory elements has a source and a drain, the virtual ground array is operative to select a set of memory elements and to fix the drains of the set of memory elements to a predetermined potential, the word lines and at least two of the select transistors select the set of memory elements and the global bit lines connect the select transistors to source and drain power supplies.

Abstract: A method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.

Abstract: A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Abstract: A memory cell has two diffusion areas in a substrate with a channel therebetween. The memory cell also includes a trapping dielectric layer at least over the channel, a gate at least above the trapping dielectric layer, and an implant in the substrate adapted to provide maximal band-to-band tunneling during erasure of charge stored in the trapping dielectric layer.

Abstract: Disclosed is a method utilizing dynamic masking for efficiently programming an N-bit memory array and, more generally, for mapping successive subsets of data segments into a succession of N-bit auxiliary bytes. When the number of programming bits in an incoming byte exceeds K, a mask maps the bit pattern of the incoming byte into sequential N-bit auxiliary bytes. A first auxiliary byte retains the bit pattern of the incoming byte up to the Kth programming bit, and the remaining bit positions of the first auxiliary byte exhibit a state complementary to the programming bits. A second auxiliary byte retains the bit pattern of the incoming byte starting with the first location after the Kth programming bit and continuing up to the Kth additional programming bit (if any); all remaining bit positions of the second auxiliary byte (including the bit positions that contained programming bits in the first auxiliary byte) exhibit the complementary state.

Abstract: A programmable, read only memory device includes two diffusion areas in a substrate and a channel formed therebetween, an oxide-nitride-oxide (ONO) layer comprising a first oxide layer overlaid by a nitride layer overlaid by a second oxide layer, the nitride layer having a thickness of 100 Angstroms or less and having two charge storage areas therein, each having a narrow width so that, during a read operation, current flows under the charge storage area not being read and a gate.

Abstract: A method for erasing a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.