Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage of the bit at least partially back to the previous threshold voltage.

Abstract: A symmetric segmented array has select transistors and column select transistors. At least one of the select and/or column select transistors is a low threshold voltage device. Alternatively, at least one select transistor and/or column select transistor of the array has a channel length shorter than a standard channel length of a process.

Abstract: A memory array includes a first plurality of metal lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line. The memory also includes a cell area formed of four segmented cell bit lines an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment.

Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optically, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off.

Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of thief selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.

Abstract: A method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, the channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, forming a non-conducting charge trapping layer at least over the channel, and managing at least one of movement of secondary electrons from the substrate towards the charge trapping layer and a punch-through voltage in the substrate by controlling a position of a concentration of an electron acceptor dopant in the substrate.

Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is onboard the die containing the memory array, but not a cell within the memory array.

Abstract: A charge pump regulator for providing a constant boosted voltage at the output of a charge pump includes: 1) a charge pump; 2) a clamping regulator; and 3) a clamping transistor. Certain preferred embodiments further include an auxiliary charge pump that provides a voltage above VDD or below ground to the clamping regulator. The clamping transistor provides a voltage supply level (Vsupp) to the oscillating clock signal generator which uses Vsupp to drive the oscillating clock signals that charge the energy injection capacitors of the charge pump between Vsupp and a reference voltage (Vref). The invention includes regulators for use with positive and negative charge pumps.

Abstract: A method of enhancing erasure of a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer includes programming the cell to minimize the width of a trapping region within the charge trapping layer by reading with a minimum voltage on the gate in a direction opposite that of programming.

Abstract: An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded.

Abstract: An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.

Abstract: A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

Abstract: A nitride programmable read only memory (NROM) cell with a pocket implant self-aligned to at least one bit line junction. Alternatively, the bit line junction(s) can have a thin area of effective programming and erasing located nearby. Further alternatively, the channel can have a threshold voltage level implant which has a low voltage level in a central area of the channel and which has a peak of high voltage level near at least one of the bit line junctions. With one pocket implant, the NROM cell stores one bit. With two pocket implants, the NROM cell stores two bits.

Abstract: An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.

Abstract: A regulator circuit to deliver a regulated boosted voltage VPP from a charge pump to electrodes of the cells of a non-volatile memory (NVM) array, such as an EPROM, integrated circuit device. The regulator includes a differential amplifier operating from a VDD voltage lower than VPP that drives a gain stage whose output is to a current mirror operating from the boosted VPP voltage. The current mirror output is taken across a voltage divider as the regulated output of the circuit. The differential amplifier has one input at a fixed voltage and the other being a feedback voltage from the voltage divider to control the gain of the differential amplifier and thereby regulate the output of the gain stage and current mirror in response to a variable load current of the integrated circuit device.

Abstract: A method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer. The step of decoupling can include the step of minimizing the injection of the non-channel electrons into the charge trapping layer. Alternatively, it includes the step of minimizing the generation of the non-channel electrons. The present invention includes cells which have minimal injection of non-channel electrons therein.

Abstract: A symmetric, segmented array includes select transistors and a regulated voltage supply. At least one select transistor is connected to each diffusion bit line. The regulated voltage supply is connected to the gates of the select transistors. The regulated voltage defines the voltage that the selected transistors provide to the diffusion bit lines. Alternatively, the array includes transistors connected to the metal bit lines and a regulated voltage supply connected to the gates of the transistors. The regulated voltage defines the voltage that the transistors provide to the metal bit lines.

Abstract: A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed of a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steeps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Abstract: A nitride programmable read only memory (NROM) cell has an oxide-nitride-oxide layer over at least a channel and a pocket implant self-aligned to at least one bit line junction. The cell also includes at least one area of hot electron injection within the ONO layer and over the pocket implant and at least one area of hot hole injection generally self-aligned to the area of hot electron injection.

Abstract: A symmetric memory array includes a multiplicity of repeating segments formed into rows and columns. Each segment includes a cell area formed of four segmented cell bit lines an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment. The array additionally includes one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively.