Abstract: A cleaning solution used in processes of fabricating semiconductor devices is disclosed.

Abstract: An apparatus, method and computer program product for a hard disk drive defect detection system. In one embodiment, a method of detecting defects on the surface of a disk having a plurality of tracks is recited. The method comprises reading, one or more times, the servo bits for a plurality of sectors and determining a burst measure for at least one sector, where the burst measure is a function of the burst signals for the sector. This method further comprises determining a reference value, where the reference value is a function of the burst signals of the plurality of sectors, and comparing the burst measure of at least one sector to the reference value to identify a potential defect. In one embodiment, a sector is mapped as defective where its burst measure differs from the reference value by at least 5 percent.

Abstract: The present invention is a method and system to optimize a write channel in a hard disk drive. The method comprises providing a disk having a at least one side with a plurality of tracks, and selecting a target track from the plurality of tracks. Data is written at least once on a predetermined plurality of tracks adjacent to either side of the target track and on the target track. Data is also written a predetermined number of times on tracks immediately adjacent to the target track. Data written on the predetermined plurality of tracks adjacent to either side of the target track and on the target track is then read. The process then determines if a number of errors on the tracks is greater than a predetermined criteria, if so, a write current value of the write channel is decreased, otherwise the write current value is increased.

Abstract: The present invention is a method and system to determine a quality of a head in a hard disk drive. The method comprises providing a disk having a at least one side with a plurality of tracks, writing on a predetermined track on the plurality of tracks and reading a profile of the predetermined track to provide a first profile value. The head is then moved to an adjacent track where it writes on the adjacent track. A profile of the predetermined track is then read to provide a second profile value. A quality of the head can then be determined based on the first and second values.

Abstract: A method of fabricating a non-volatile memory device includes the steps of forming a lower conductive layer on a substrate, forming a lower and an upper sacrificial patterns on the substrate with the lower conductive layer, wherein the lower and upper sacrificial patterns include a trench exposing the lower conductive layer, forming mask spacers on sidewalls of the upper and lower sacrificial patterns, using the mask spacers and the upper sacrificial pattern as an etch mask, etching the exposed lower conductive layer to form a lower conductive pattern exposing the substrate, forming a plug conductive layer covering an entire surface of a substrate with the lower conductive pattern, and planarizingly etching the plug conductive layer until the lower sacrificial pattern is exposed, thereby forming a source plug in a gap region between the mask spacers that is connected to the substrate.

Abstract: A non-volatile SONOS memory device includes a semiconductor substrate having a source region and a drain region. A channel is formed between the source region and the drain region. A gate insulation layer including a nitride layer is formed over the channel, and a gate is formed over the gate insulation layer. The channel is a stepped channel including a top part, an inclined part and a bottom part.

Abstract: A composition for a bottom-layer resist, having superior anti-refractivity and dry-etch resistance for use in a bi-layer resist process employing a light source at a wavelength of 193 nm or below, is disclosed.

Abstract: A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is disposed on the semiconductor substrate at one side of the control gate pattern. A gate insulation pattern is interposed between the selection gate electrode and the semiconductor substrate, and between the selection gate electrode and the control gate pattern. A cell channel region includes a first channel region defined in the semiconductor substrate under the selection gate electrode and a second channel region defined in the semiconductor substrate under the control gate electrode.

Abstract: A data storage unit of an image compression device for compressing motion picture frame is provided. The data storage unit comprises: a previous frame field having a plurality of slices; a decoded frame field having a plurality of slices; and a current frame field having a plurality of slices, wherein the previous frame field stores a previously decoded image and the decoded frame field stores a currently decoded image, wherein the number of slices of the previous frame field is greater than the number of slices of the decoded frame field and the current frame field.

Abstract: The present invention provides an asymmetric communication system having an echo canceller and a method for downloading a filter coefficient to the echo canceller. The echo canceller is a kind of a finite impulse response (FIR) filter for calculating a correlativity between an echo input signal and an echo output signal to generate a filter coefficient. The echo canceller includes a delay line block for delaying an echo input signal for a predetermined interval to generate a delay signal, a filter coefficient table block for sequentially shifting filter coefficients which are sequentially stored in a shift register, and a multiplication and accumulation block for multiplying and adding the delay signal of the delay line block by a filter coefficient that is an output of the filter coefficient table block to generate an echo-cancelled echo output signal. The filter coefficient has the shift rate ratio between the RT mode to the CO mode of the asymmetric communication system.

Abstract: A photosensitive polymer including silicon and a resist composition using the same are disclosed. The photosensitive polymer has the following formula 1.

Abstract: A non-volatile memory cell having a floating gate and a method of forming the same. The non-volatile memory cell includes a device isolation layer that is formed in a semiconductor substrate and defines an active region. A floating gate is disposed over the active region and is comprised of a plurality of first conductive patterns and a plurality of second conductive patterns that are alternately stacked. A first insulation layer is disposed between the floating gate and the active region. One of the first conductive pattern and the second conductive pattern protrudes to form concave and convex sidewalls of the floating gate. Therefore, a surface area of the floating gate increases, thereby raising coupling ratio between the floating gate and the control gate electrode. As a result, an operating voltage of the non-volatile memory cell can be reduced.

Abstract: A cleaning solution selectively removes a titanium nitride layer and a non-reacting metal layer. The cleaning solution includes an acid solution and an oxidation agent with iodine. The cleaning solution also effectively removes a photoresist layer and organic materials. Moreover, the cleaning solution can be employed in tungsten gate electrode technologies that have been spotlighted because of the capability to improve device operation characteristics.

Abstract: A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and is disposed at the memory cell area. The OTP ROM capacitor has a lower electrode, an upper intermetal dielectric, and an upper electrode which are stacked in the order named. The OTP ROM capacitor is disposed on the MOS transistor, and the floating gate electrode and the lower electrode are connected by a floating gate plug to constitute an electrically insulated conductive structure. The upper intermetal dielectric is made of at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride and may be disposed on an entire surface of the semiconductor substrate. A capacitor formed together with the OTP ROM is disposed at the peripheral circuit region.

Abstract: A method, apparatus, and computer program product for a hard disk drive servomechanism. In one embodiment, the apparatus comprises a disk which has a surface, a spindle motor that rotates the disk, a transducer which can write information onto the disk and read information from the disk, and an actuator arm that can move the transducer across the surface of the disk. The apparatus further includes a controller. The controller can determine a seek length from a first track to a second track, determine a seek time based on the seek length, scale the seek time in response to a velocity error between a calculated velocity and a design velocity for the seek length, and control the actuator arm to move the transducer across the disk surface from the first track to the second track using an acceleration trajectory.

Abstract: A method for fabricating a semiconductor device, including forming a gate insulating film and a gate electrode film on a semiconductor substrate, and patterning the gate electrode film to form a gate electrode. A portion of the gate insulating film is removed to form an undercut region beneath the gate electrode. A buffer silicon film is formed over an entire surface of the resultant substrate to cover the gate electrode and to fill the undercut region. The buffer silicon film is selectively oxidized to form a buffer silicon oxide film.

Abstract: A grilling apparatus is provided with a grill of an improved structure, thus preventing food from being burnt due to overheating of the grill and reducing a cooking period to cook the food. The grilling apparatus includes a cabinet defining an external appearance of the grilling apparatus. An opening is formed at a top of the cabinet. A grill comprises a plurality of pipes, is set in the cabinet through the opening of the cabinet, and is downwardly bent, at a portion thereof, to form a food supporting part supporting opposite side surfaces of the food. The grilling apparatus includes two water tanks which are connected to respective ends of the plurality of pipes to supply the water to the plurality of pipes. One or more heating units are provided at predetermined positions adjacent to respective sides of the food supporting part in the cabinet so as to irradiate heat to the food supporting part.

Abstract: A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

Abstract: A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover a transfer gate and a floating diffusion layer. Therefore, the floating diffusion layer may not be attacked by an etching during a formation of sidewall spacers of various gates or by ion implantation during a formation of a junction region of a DDD or LDD structure, thus reducing a leakage current and a dark current at the floating diffusion layer.