Abstract: Methods of simultaneously forming MOS transistors and a capacitor on a substrate having gate insulation layers of varying thicknesses. A method includes forming field regions in a substrate to define a first transistor region, a capacitor region, and a second transistor region, forming a first gate stack in the first transistor region and a lower electrode in the capacitor region, and forming an upper electrode on the lower electrode with a dielectric layer interposed therebetween and a second gate stack in the second transistor region.

Abstract: A method, apparatus, and computer program product for linearizing a position error signal of a transducer in a hard disk drive. In one embodiment, a disk including a first plurality of tracks each includes first and second servo bursts defining a track reference line, and a second plurality of the first plurality of tracks on the disk each includes third and fourth servo bursts defining a second plurality of different position offsets from the track reference line of the second plurality of tracks. Each of the second plurality of different position offsets being at a different value than any other position offset. The second plurality is no greater than the first plurality. The second plurality of different position offsets are used for linearizing a position error signal.

Abstract: An apparatus and method for testing a computer system by utilizing a Field Programmable Gate Array (FPGA) and programmable memory modules is provided. The apparatus includes a controller, a plurality of programmable memory modules, and an FPGA. Each programmable memory module stores configuration data of peripheral devices of the computer system in corresponding versions, respectively, which are differentiated according to functions of the computer system. Each memory module stores configuration data about a PCI host controller, a memory controller, a PLL, an interrupt controller, an arbiter, a UART, or a timer. The FPGA is programmed according to data stored in one memory module selected from among the programmable memory modules. Therefore, in the apparatus, the FPGA does not contain a bus bridge circuit, so that the FPGA has an increased programmable area and can be easily connected even with peripheral devices requiring many input and output ports.

Abstract: A frequency synthesizer that improves a unique DDS characteristic, while maintaining a circuit scale (ROM size) of a direct digital synthesizer (DDS). A first digital signal generator generates a quantized frequency signal, and a second digital signal generator generates a frequency signal having a fine frequency resolution and many spurious signals as compared with the first digital signal generator. A filter performs band rejection on an output of the second digital signal generator, and a mixer mixes an output of the first digital signal generator with an output of the filter.

Abstract: A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked. A lower insulating pattern, which is covered with the charge storage layer and thicker than the tunnel insulating pattern, is disposed on the semiconductor substrate beside the tunnel insulating layer. A heavily doped region including impurities of the same type as the semiconductor substrate is disposed in the semiconductor substrate under the tunnel insulating pattern.

Abstract: An integrated circuit device having multiple communication modes is provided. The integrated circuit device includes a transceiver coupled to first and second data lines. The integrated circuit device further includes a voltage control circuit. The voltage control circuit determines whether or not an external device is connected to the integrated circuit device. In the case where the external device is connected to the integrated circuit device, the voltage control circuit controls the voltage of the first data line so as to cause the external device to not recognize the integrated circuit device for a predetermined time.

Abstract: A tamper-resistant method for preventing tampering using a glitch attack and a data processing system using the same are provided. The method includes reading out a first data from a region of the memory assigned by an address; reading out a second data from the region of the memory assigned by the address; determining whether the first data is identical to the second data; and fetching by the processor either one of the first and second data when the first data is identical to the second data.

Abstract: A refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same is provided. The refresh circuit includes a refresh pulse generating unit for receiving a clock signal to generate first and second refresh signals, a standby refresh signal generating unit for receiving the second refresh signal and a chip select signal to generate a standby refresh signal, the chip select signal representing an active state and a standby state of the semiconductor memory device, and a word-line pulse generating unit for receiving the first refresh signal and the standby refresh signal to generate a word-line driving signal. A pulse width of the word-line driving signal generated at the standby state is longer than that generated at the active state resulting in a sufficient refresh time at each memory cell.

Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

Abstract: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated. The sizes of the primary and supplementary spare areas are determined by the number of defects generated upon initialization. The information on the sizes of the spare areas, and the remainder state information representing the degree of use of the spare areas, are recorded, so that the spare areas can be efficiently managed.

Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Abstract: A portable device includes a display unit, a memory, input keys, and a microprocessor. The display unit has a character window, which includes a selecting character window and a selected character window, for displaying characters. One character line including the character which has virtual coordinates indicated by a cursor is displayed in the selecting character window, and the character selected from the characters in the selecting character window is displayed in the selected character window by input keys. The memory stores the characters having intrinsic virtual coordinates, and several input keys serve for navigating across the characters by using the virtual coordinates of the characters to select the characters. The microprocessor controls the display of the characters on the display unit in correspondence to the input of the input keys.

Abstract: A semiconductor memory device employs a power supply system in which a first power supply voltage supplied to a cell area is separated from a second power supply voltage supplied to a peripheral circuit area. Particularly, during a wafer burn-in test operation mode, the first power supply voltage supplied to the cell area is higher than the second power supply voltage supplied to the peripheral circuit area. If a wafer burn-in test operation is performed under the second power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be shut off.

Abstract: An atomic layer deposition apparatus and a method of operating the same are provided. The atomic layer deposition apparatus is used to deposit an atomic layer by repeatedly supplying and purging a process gas, and includes a chamber used for depositing an atomic layer, a gas injection hole through which the process gas is supplied to the chamber, a first outlet through which particles or remnants are removed from the chamber when supplying the process gas, and a second outlet through which exhaust gas is discharged from the chamber when purging the process gas.

Abstract: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated. The sizes of the primary and supplementary spare areas are determined by the number of defects generated upon initialization. The information on the sizes of the spare areas, and the remainder state information representing the degree of use of the spare areas, are recorded, so that the spare areas can be efficiently managed.

Abstract: A radio system is disclosed for supporting a greater number of users than can be supported in a conventional CDMA system that supports multiple users. The radio system is a hybrid system combining elements of conventional spread spectrum techniques. The system may be defined as a parallel hopping hybrid direct sequence (DS)/slow frequency hopping (SFH) code division multiple access (CDMA) system in combination with a DS/CDMA system, frequency hopping (FH)/CDMA system and a multi-carrier system.

Abstract: Disclosed is a method for performing a handoff from an async base station to a sync base station when a mobile station with async and sync demodulation modules travels from a present cell of the async base station to a cell of the sync base station, the method including the steps of: the mobile station driving the sync demodulation module for a given idle sleep time to acquire and maintain the timing of the sync base station, during an operation in the cell of the async base station; during the handoff, the mobile station measuring the strengths of pilot signals from the adjacent sync base stations based on the acquired timing, and sending the measurement results to the async base station; the mobile station receiving from the async base station information necessary to establish a traffic channel with the sync channel; and the mobile station performing handoff to the sync base station according to the information necessary to establish the traffic channel.

Abstract: A circuit for at least substantially eliminating at least one external interference signal from a radio communications signal received by a code division multiple access (CDMA) mobile phone including a receiving terminal and a low noise amplifier comprises: a plurality of damping devices operatively coupled between the receiving terminal and the low noise amplifier; a plurality of switches respectively operatively coupled between the plurality of damping devices and the receiving terminal; an interference detector operatively coupled to the receiving terminal for detecting the at least one external interference signal from the received radio communications signal; and a switch driver operatively coupled between the plurality of switches and the interference detector, the switch driver generating a switching signal in response to the interference detector to select at least one of the switches in accordance with the at least one detected interference signal in order to vary a gain associated with the received

Abstract: A system and method for pursuing a missing cellular telephone are provided. The cellular telephone analyzes a control signal received from a mobile communication network. If the analyzed control signal corresponds to a missing mode setting signal, the cellular telephone enters a missing mode and transmits a position signal representing the current location at regular intervals. In the meantime, upon receipt of a missing mode release signal from the mobile communication network, the cellular telephone releases the missing mode. Further, the cellular telephone transmits the position signal at regular intervals beginning at termination of an incoming or outgoing call, when the missing cellular telephone answers the incoming call or makes the outgoing call in the missing mode.

Abstract: A radio system is disclosed for supporting a greater number of users than can be supported in a conventional CDMA system that supports multiple users. The radio system is a hybrid system combining elements of conventional spread spectrum techniques. The system may be defined as a parallel hopping hybrid direct sequence (DS)/slow frequency hopping (SFH) code division multiple access (CDMA) system in combination with a DS/CDMA system, frequency hopping (FH)/CDMA system and a multi-carrier system.