Abstract: A storage system and method for recovering data corrupted in a host memory buffer are provided. In one embodiment, a storage system is provided comprising a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to receive a logical-to-physical map from a volatile memory of a host for storage in the storage system's non-volatile memory; determine if there is an error in an entry in the logical-to-physical map; in response to determining that there is no error in the logical-to-physical map, store the logical-to-physical map in the non-volatile memory; and in response to determining that there is an error in an entry in the logical-to-physical map, attempt to recover the entry from a location in the storage system before storing the logical-to-physical map in the non-volatile memory. Other embodiments are provided.

Abstract: A storage device with a memory may implement command throttling in order to control power usage. The throttling may be based on modifications of certain memory parameters, such as a reduction in clock rate, bus speed, operating voltage, or command type changes. The throttling may be performed at a back end or memory interface of the storage device such that the memory interface receives un-throttled commands and can optimally throttle all of the commands from the front end.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.

Abstract: A storage device may utilize a host memory buffer for re-ordering commands in a submission queue. Out of order commands in a submission queue that uses host virtual buffers that are not the same size may be difficult to search. Accordingly, commands in a submission queue may be correctly ordered in a host memory buffer before being put into the host virtual buffers. When the commands are in order, the search operation for specific data is improved.

Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.

Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.

Abstract: A system and method for compacting data in a non-volatile memory system that may reduce the need for control data updates is described. The method may include copying valid data from a source block to a destination block, and also writing new host data to the destination block, such that the offset position in the destination block of the copied data is the same as in the source block and fewer mapping table updates are needed for the copied data. The system may include a non-volatile memory system with a coarse granularity mapping table and a fine granularity mapping table where a controller in the non-volatile memory system is configured to only update the coarse granularity mapping table for compacted data written to a new block, but is configured to update both the fine and coarse granularity mapping tables for new host data written to the new block.

Abstract: Methods and systems for managing data storage in a non-volatile memory system are disclosed. The method may include receiving data, determining a data classification for the received data from a predetermined plurality of data classifications, writing the received data to an open block having only data of a same data classification as the determined data classification and, upon completely programming the open block, associating an epoch indicator where the epoch indicator defines a time period within which the block was created. When a block reclaim trigger is detected, only data within a same data classification and epoch may be reclaimed. An incrementing epoch indicator identifies a predetermined time granularity and is assigned to data such that earlier data and newer data are distinguishable. A system to implement the method may include a non-volatile memory and a controller configured to track and apply epoch and data-type classification information for data.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from peripheral circuitry for an array. A portion of target data received by a shadow data register may be copied to a corresponding write buffer data register while the shadow data register receives the portion of the target data.

Abstract: A voltage regulator circuit is provided in which voltage overshoots are quickly dissipated using a discharge path which is connected to an output of the voltage regulator. Circuitry for controlling the discharge path is provided using internal currents of an error amplifier to provide a space-efficient and power-efficient design with a fast response. Moreover, hysteresis can be provided to avoid toggling between discharge and no discharge, and to avoid undershoot when discharging the output. A digital or analog signal is set which turns the discharge transistor on or off. A current pulldown may be arranged in the discharge path.

Abstract: Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.

Abstract: Techniques for managing the distribution of power among competing electronic devices such as semiconductor die are presented. Each device may be connected to a common power supply and sources a current on a load bus based on an estimated current consumption of a next desired state. However, before doing this, the device performs an internal check to determine whether there is a sufficient available current. The device decreases a logical value of the system current specification by the increase in current which is desired. A resulting voltage (Vspec) is compared to a voltage of the load bus (Vcontact). If Vcontact<=Vspec, the device sources current on the load bus to signal other devices that the available current is reduced. If a conflict is detected with another device, an arbitration process is performed. A linear or binary search algorithm can be used based on a respective device priority.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for redundancy mapping. A controller is configured to determine that one or more defects affect a subset of a first group of cells and a subset of a second group of cells of a non-volatile memory medium. A non-volatile memory medium may include a plurality of groups of cells, and redundant groups of cells may be available for replacing defective groups of cells. A controller is configured to store a mapping between affected subsets of first and second groups of cells and a redundant group of cells for a non-volatile memory medium. A controller is configured to read data for a first group and/or second group of cells by referencing a mapping and using a redundant group of cells.

Abstract: A mobile device and method for synchronizing use of the mobile device's communications port among a plurality of applications are provided. In one embodiment, a mobile device is provided comprising a communications port configured to connect with a mobile device accessory and a processor. The processor is configured to synchronize requests from a plurality of applications running on the mobile device to prevent application(s) from sending a request that would interrupt an ongoing data transfer between the mobile device accessory and another application. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Systems and methods for decoupling host commands in a non-volatile memory system are disclosed. In one implementation, a non-volatile memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to translate a first command that is formatted according to a communication protocol to a second command that is formatted generically, store the first command in an expected queue, and store the second command in the expected queue with a command priority. The controller is further configured to execute the second command based on the command priority, translate a result of the executed second command into a format according to the communication protocol, and transmit the result of the executed second command in the format according to the communication protocol to a host system dependent upon a position of the first command in the expected queue.

Abstract: A memory system and method for fast firmware download are provided. In one embodiment, a memory system is presented comprising non-volatile memory, volatile memory, and a controller. The controller is configured to receive a boot loader and firmware; store the boot loader and firmware in the volatile memory; execute the boot loader, wherein executing the boot loader causes the controller to read the firmware from the volatile memory, decompress the firmware, and store the decompressed firmware in the volatile memory; and copy the compressed firmware from the volatile memory to the non-volatile memory. Other embodiments are provided.

Abstract: A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.

Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

Abstract: A non-volatile memory system may include a plurality of memory dies and a controller that is configured to write data into the memory dies according to a multi-die interleave scheme. A total number of the dies may be a non-multiple of a die component number of the interleave scheme. The controller may select abstract address based on a virtual die layout, and translate the abstract address to actual physical addresses. The translation may identify actual blocks located in different rows of blocks. The controller may also read data sets from the memory dies. To do so, the controller may translate an abstract address to actual physical addresses, which may similarly identify actual blocks located in different rows of blocks.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.