Abstract: Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc.

Abstract: A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. A programming operation avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn?1) are read. The read operation for WLn uses multiple read voltages—one for each data state on WLn?1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell.

Abstract: One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such high risk word lines to a location outside the MLC block where the copy is maintained. Subsequent read requests for the data may be directed to the copy of the data outside the MLC block.

Abstract: A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements.

Abstract: Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.

Abstract: Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.

Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.

Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.

Abstract: Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify are disclosed. According to one aspect, a method for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify includes performing a program verify operation after a write to a non-volatile memory, where the program verify mechanism reports a pass or fail based on an existing measurement threshold value, and dynamically adjusting the measurement threshold value used by subsequent program verify operations based on the results of previous program verify operations.

Abstract: A data storage device includes a controller operatively coupled to a non-volatile memory. The non-volatile memory includes a plurality of blocks. When the controller is configured to operate according to a first mode, a portion of a first redundancy block of the plurality of blocks stores first redundancy data corresponding to a first group of multiple data portions. The multiple data portions stored in multiple blocks of the plurality of blocks. When the controller is configured to operate according to a second mode, the portion of the first redundancy block stores second redundancy data corresponding to a single block of the plurality of blocks.

Abstract: A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages.

Abstract: In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge.

Abstract: Methods for enabling software from a storage-capable device including the steps of: loading, by a host system operationally connected to the storage-capable device, software from an authenticatable storage area residing in the storage-capable device; validating the software; and installing the validated software, wherein the validated software provides an interface between the host system and the storage-capable device. In some embodiments, the software is enabling software, the method further including the step of loading, by the host system, device-functionality software from the authenticatable storage area. In some embodiments, the method further includes the steps of: validating the device-functionality software; and enabling the validated device-functionality software.

Abstract: A storage module and method are disclosed for determining whether to back-up a previously-written lower page of data before writing an upper page of data. In one embodiment, a storage module receives a command to write an upper page of data to memory cells that have already been programmed with a lower page of data. The storage module determines whether a command to protect the lower page of data was previously received. The storage module backs-up the lower page of data in another area of the memory before writing the upper page of data to the memory cells only if it is determined that the command to protect the lower page of data was previously received. The storage module then writes the upper page of data to the memory cells.

Abstract: An erase operation for a memory cells in a block provides a consistent and sufficient erase depth regardless of the number of programmed word lines in the block. A lower erase-verify voltage is used for a first-programmed word line of a set of word lines than for remaining word lines in the set. As a result, the resistance of a memory cell of the first-programmed word line dominates during sensing of the NAND string so that the number of erase loops can be controlled in a predictable way regardless of the number of programmed word lines. The lower erase-verify voltage can be optimized so that it does not change the number of erase loops to complete an erase operation, compared to the case where a common erase-verify voltage is used on all word lines.

Abstract: A system for optimizing drive strength may be utilized for identifying the maximum data transfer rate for different devices and different device configurations. The drive strength may be optimized for input/output (I/O) devices by measuring voltage drops on I/O power supply using different test patterns. The maximum drive strength is identified that satisfies a limit or threshold for the allowed voltage drop level. The test pattern may include a simultaneous toggling of each I/O device. A slew rate for the device may be utilized along with the drive strength for identifying the maximum data transfer rate.

Abstract: A non-volatile memory system includes a memory section having a non-volatile cache portion storing data in a binary format, a primary user data storage section that stores user data in multi-state format, and an update memory area where the memory system stores data updating user data previously stored in the primary user data. The memory system allows a maximum number of blocks for use in the update memory area. When the memory system receives updated data corresponding to user data already written into the primary user data storage section, it determines whether a block of memory is available in the update memory area. In response to determining that a block of memory is not available in the update memory area, the system determines a block of the update memory to remove from the update memory; copies the data content of the determined update block into the cache portion of the memory section; and subsequently writes the updated data into the update memory.

Abstract: Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. After completion of a full programming pass, a verify test is performed to identify cells for which reprogramming is warranted. The reprogramming includes a single program pulse for each target data state, where each program pulse is longer than in the full programming pass. The pulse widths can be optimized based on factors such as a programming speed or a threshold voltage distribution width from the full programming pass.

Abstract: The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.

Abstract: Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.