Patents Assigned to SanDisk Technologies Inc.
  • Method of making a multi-tier memory device with rounded joint structures
    Patent number: 12324150
    Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: June 3, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Tsutomu Imai, Nao Nagase, Chiko Kudo, Sadao Fukuno
  • Multi-tenant device read command service balancing
    Patent number: 12314585
    Abstract: In order to ensure that a bandwidth allocated to each tenant of a plurality of tenants of a data storage device is maintained, a controller of the data storage device may split a large read command, received from a host device, into a plurality of chunks, where each chunk corresponds to a distinct portion of the split large read command. Because the allocated bandwidth for a tenant is static, one or more chunks of the plurality of chunks, up to the allocated bandwidth, are executed, such that the bandwidth required to perform the one or more chunks does not exceed the allocated bandwidth for the particular tenant. Split information is added to the plurality of chunks in order to maintain coherency when executing the one or more chunks. Therefore, the agreed-upon allocated bandwidth for each tenant is maintained while performing large read commands requiring more bandwidth than allocated.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: May 27, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Elkana Richter, Shay Benisty, Amir Segev
  • ZNS protection with small SLC cache using zone groups
    Patent number: 12314132
    Abstract: The present disclosure generally relates to achieving an acceptable uncorrectable bit error rate (UBER) using a dual temporary data protecting approach and a small SLC cache by adding a temporary XOR protection to zone-groups rather than storing another copy of the zone within the drive. The parity data can be stored with the user data (e.g., as part of the zone-group, effectively increasing zone-group size by 1) or in a separate location, e.g., in an SLC block or another separate MLC block.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: May 27, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Karin Inbar, Stephen Gold, Liam Parker
  • Three-dimensional memory device containing ferroelectric-assisted memory elements and method of making the same
    Patent number: 12317502
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of charge storage elements, a vertical semiconductor channel, a ferroelectric material layer located between the vertical stack of charge storage elements and the vertical semiconductor channel, and a blocking dielectric layer located between the ferroelectric material layer and the vertical semiconductor channel. A tunneling dielectric layer is located between at least one of the electrically conductive layers and the vertical stack of charge storage elements.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: May 27, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Ramy Nashed Bassely Said, Adarsh Rajashekhar, Senaka Kanakamedala, Raghuveer S. Makala
  • QoS optimization by using data tracking module
    Patent number: 12299289
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When data received by the controller, from a host device or from a non-volatile memory of the data storage device, the controller maintains table tracking the location of the data. The table may include a current location of the data in a volatile memory of the controller or the data storage device as well as the current location of the data a latch of the non-volatile memory. The table may further associate the location with a logical block address, such that when the host device requests the data not yet programmed to the non-volatile memory or data that is part of a data relocation operation, the controller may utilize the table to locate the relevant data and provide the data to the host device.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: May 13, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Michael Ionin, Alexander Bazarsky, Judah Gamliel Hahn
  • Secure wear levelling of non-volatile memory based on Galois field circuit
    Patent number: 12300295
    Abstract: Wear levelling techniques based on use of a Galois field for the logical to physical translation of data addresses for a non-volatile memory, such as an MRAM-based memory, are presented. This not only provides a wear levelling technique to extend memory life, but also adds an additional layer of security to the stored memory data. More specifically, the following presents embodiments for secure wear levelling based on a Galois field having an order based on the size of the memory. To further improve security, a randomly generated rotation of the logically address based on the Galois field can also be used.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: May 13, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Martin Hassner, Mark Branstad
  • Enhanced end to end system failure recovery
    Patent number: 12298846
    Abstract: In order to guarantee data validity of data read from a memory device of the data storage device to a host device, a controller of the data storage device may calculate a cyclic redundancy code (CRC) signature of the decoded data and compare the CRC signature of the decoded data with a CRC signature of the data. The CRC signature of the data is generated during a write operation of the data to the memory device. Rather than returning an uncorrectable error correction code error (UECC) error to the host device when the CRC signature of the decoded data does not match the CRC signature of the data, the controller executes the read command again. By using a different buffer to store the decoded data, the controller may confirm whether the error stemmed from the read path or the error was not from the read path.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: May 13, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Michael Ionin, Alexander Bazarsky, Judah Gamliel Hahn
  • Cross-point array refresh scheme
    Patent number: 12300296
    Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: May 13, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Michael Nicolas Albert Tran, Michael K. Grobis, Ward Parkinson, Nathan Franklin
  • Data storage device and method for performance-dependent storage of parity information
    Patent number: 12292796
    Abstract: A data storage device can store data and parity information for the data in its memory. In some storage methodologies, data and parity information are striped across a plurality of memory dies (e.g., in a redundant array of independent drives (RAID) configuration). That way, if one of the memory dies fails, the data or the parity information can be reconstructed from the other memory dies. These embodiments recognize that because parity information is used relatively infrequently, the parity information can be stored in locations in the memory that have a relatively-worse performance than other areas of the memory. This can increase performance of the memory in situations where the parity information does not need to be read.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: May 6, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Daniel J. Linnen, Ramanathan Muthiah, Noor Mohamed Aa
  • Storage system and method for implementation of symmetric tree models for read threshold calibration
    Patent number: 12293796
    Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: May 6, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Alexander Bazarsky, David Avraham, Nika Yanuka, Idan Alrod
  • Non-volatile memory with layout adaptive problematic word line detection
    Patent number: 12293800
    Abstract: In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: May 6, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Xuan Tian, Liang Li, Dandan Yi, Jojo Xing, Vincent Yin
  • Memory device with reinforcement learning with Q-learning acceleration
    Patent number: 12293109
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives. A data storage device includes a controller, one or more volatile memory locations, and one or more non-volatile memory locations. Computations, including reinforcement learning algorithms, may be completed by the controller using the one or more non-volatile memory locations. Data associated with reinforcement learning is stored in a table on one or more planes of the non-volatile memory, where the results from the computations update the table with the relevant values. The data in the table are aligned to one or more wordlines, such that sensing the wordline senses all the data stored in the table.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 6, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Ran Zamir, Ofir Pele, Stella Achtenberg, Omer Fainzilber
  • Data storage device and method for improving asynchronous independent plane read (AIPR) utilization
    Patent number: 12293085
    Abstract: Some data storage devices have a plurality of memory dies that can be read in parallel for certain types of read requests. Read requests pertaining to a garbage collection operation are often generated sequentially and, thus, are not eligible for parallel execution in the memory dies. In an example data storage device presented herein, such read requests are consolidated and sent to the memory for execution in parallel across the memory dies.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: May 6, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Pradeep Seetaram Hegde, Ramanathan Muthiah, Nagaraj Dandigenahalli Rudrappa, Vimal Kumar Jain
  • Apparatus and methods for smart verify with adaptive voltage offset
    Patent number: 12293797
    Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: May 6, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Longju Liu, Sarath Puthenthermadam, Jiahui Yuan
  • Three-dimensional memory device containing templated crystalline ferroelectric memory elements and method of making thereof
    Patent number: 12289889
    Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Kartik Sondhi, Adarsh Rajashekhar, Fei Zhou, Raghuveer S. Makala
  • Housings for electronic devices and memory devices
    Patent number: 12288573
    Abstract: Embodiments of the present disclosure generally relate to housings for, e.g., memory devices and electronic devices, and to processes for forming such housings. In an embodiment, an article for housing at least a portion of an electronic device is provided. The article includes a first component comprising a thermoplastic and a biodegradable filler or polymer, and a second component disposed on at least a portion of the first component, the second component comprising a plurality of layers. The article has a scratch visibility load of about 200 gms or more, an electrostatic discharge static voltage of about 100 V or less, a thermal conductivity of about 0.28 W/mK or more, or combinations thereof.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Vishnu Chandar Janakiraman, Mutharasu Devarajan, KL Bock
  • Multi-tier memory device with rounded joint structures and methods of making the same
    Patent number: 12289886
    Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Nao Nagase, Chiko Kudo, Tsutomu Imai
  • Three-dimensional memory device containing deformation resistant trench fill structure and methods of making the same
    Patent number: 12288755
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner having the first Young's modulus, a vertically alternating sequence of insulating plates and dielectric material plates at least partially laterally surrounded by the dielectric moat fill structure, and an interconnection via structure vertically extending the vertically alternating sequence.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventor: Koichi Matsuno
  • Adaptive single-side erase to improve cell reliability
    Patent number: 12287974
    Abstract: A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Zhenni Wan, Bo Lei
  • Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making the same
    Patent number: 12289887
    Abstract: A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer. The barrier layer may be a dielectric blocking barrier layer.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Peter Rabkin, Masaaki Higashitani