Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.

Abstract: A method for detecting faults in a memory system includes performing an operation on at least one memory cell of the memory system. The method also includes receiving, during performance of the operation, a first clock cycle count for a first pulse of a charge pump associated with the at least one memory cell. The method also includes receiving, during performance of the operation, a second clock cycle count for a second pulse of the charge pump. The method also includes determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.

Abstract: A memory array is provided that includes a first memory level having a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element, and a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells.

Abstract: An apparatus performs vector matrix multiplication (VMM) for an analog neural network (ANN). The apparatus includes a column of NAND flash cells in series, where each NAND flash cell includes a control gate; a bit line connected to the column of NAND flash cells, where a current drawn from the NAND flash cells flows to the bit line; an integrator connected to the bit line; and a controller having programmed instructions to control the column of NAND flash cells by setting the voltage of the control gate of each NAND flash cell.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.

Abstract: A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.

Abstract: A method for duty cycle error detection and correction includes receiving, during a read operation performed on a memory cell, a first data strobe signal. The method also includes generating a second data strobe signal by phase delaying the first data strobe signal. The method also includes determining, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted. The method also includes adjusting a clock signal based on a determination that the duty cycle is distorted.

Abstract: A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Abstract: A partial page sensing method and system are provided in which, while a bit line voltage (VBLC) is applied to first bit lines of a first partial page of a memory cell array, second bit lines, of a second partial page are floated. The second bit lines of the second partial page are bit lines which are interleaved with the first bit lines of the first partial page. Bit lines associated with one or more additional partial pages may be grounded or floated. A bit line associated with an additional partial page which is adjacent to one of the first bit lines may be floated.

Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.

Abstract: A memory device includes a memory module that encrypts and decrypts data with a key. To encrypt, the memory module performs a first modified XOR operation in which a ciphertext has a same logical value as a corresponding key when the data has a low logical value and the ciphertext has an inverse of the logical value of the corresponding key when the data is at a high logical value. To decrypt, the memory module performs a second modified XOR operation in which the logical value of the ciphertext forms the logical value of the data when the corresponding key is at the low logical value and the inverse of the logical value of the ciphertext forms the logical value of the corresponding data when the corresponding key is at the high logical value.

Abstract: A device, for example a memory system, is disclosed wherein two or more operational modes may be set. The clock toggle rate and ODT resistors are dynamically controlled based on one or more of a desired margin of signal integrity, performance, cooling rate, and power consumption.

Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.

Abstract: A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

Abstract: A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

Abstract: A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.