Abstract: A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristics of the memory from the outer memory holes to the inner memory holes. These difference can be accounted for by grouping the memory holes and altering the parameters of the program or verify operations based on the groupings. The bitline voltage for the inner grouping can be less than the bitline voltage for the outer groupings. The sense timing can be greater for the outer groupings relative to the inner groupings. This can result in voltage threshold for the inner groupings and outer groupings overlying each other to improve memory performance.

Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

Abstract: Non-volatile, high performance memory devices balance speed and reliability, which can include channel boosting to reduce data error rates in the memory cells. Vertical NAND strings exhibit greater program disturb (errors) the higher the wordline is on the string. The present disclosure applies a boosted bit line voltage or an increased precharge time when the programming reaches a level (wordline number) where it has been determined that errors due to program disturb may be an issue. The boost to the bit line may occur after a stored wordline value or based on a calculated number of errors at a previous wordline. In an example, the bit line stays the same as the prior world line programming operation until the likely program disturb is determined.

Abstract: A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.

Abstract: A method is provided that includes applying a read voltage to a resistance-switching memory cell to determine a first memory cell resistance, applying a first write voltage to the resistance-switching memory cell, applying the read voltage to the resistance-switching memory cell to determine a second memory cell resistance, and comparing the first memory cell resistance to the second memory cell resistance to determine that the resistance-switching memory cell is in a first memory state or a second memory state.

Abstract: The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in electrical communication with the first terminal and the second terminal, wherein the voltage difference between the first terminal and the second terminal changes the channel from a first state to a second state when a threshold voltage between the first terminal and the second terminal is exceeded, the threshold voltage being dependent on temperature. The third terminal is resistive and receives a control signal to apply heat to the pillar and modulate the threshold voltage. The switching device can be used to select the memory stack through the bitline and provide a nearly limitless current based on the threshold switching conduction providing avalanche current conduction through the switching device.

Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.

Abstract: A methodology and structure for selectively erases a group of strings in a vertical NAND memory array to account for the slow to erase memory cells in the inner strands compared to the outer strands in the group. Erase signals can be applied through both the drain side connections and the source side connections in a first step to erase the outer strings. A second erase signal can be applied to the inner strands to erase the inner strands. The second signal can be applied from just the drain side connections or through both the drain side connections and the source side connections. In another embodiment, the erase signals are applied from both the source side connections and the drain side connections to the inner strings and only from the source side connections to the outer strings.

Abstract: A methodology and structure for a encoding a data stat signal in the data lock signal, e.g., the data strobe signal such as DBQ. The data strobe signal can maintain the clock continuity, e.g., the rise and fall edges are at the timing signal, and the data inversion can be based on the amplitude of the data strobe signal. This allows the data set on the data lines, e.g., D0-D7, to either be non-inverted or inverted, to save power consumed in the memory device.

Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad.

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

Abstract: A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

Abstract: Techniques are provided for mitigating issues of memory hole mis-shape. In one aspect, one or more control circuits are configured to program a group of non-volatile memory cells from an erase state to a plurality of programmed states using a first program parameter. The one or more control circuits measure threshold voltages of the group to determine a severity of memory hole mis-shape in the group. The one or more control circuits program the group from the erase state to the plurality of programmed states using a second program parameter selected based on the severity of the memory hole mis-shape in the group.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.

Abstract: Techniques are provided for mitigating issues of memory hole mis-shape. In one aspect, one or more control circuits are configured to program a group of non-volatile memory cells from an erase state to a plurality of programmed states using a first program parameter. The one or more control circuits measure threshold voltages of the group to determine a severity of memory hole mis-shape in the group. The one or more control circuits program the group from the erase state to the plurality of programmed states using a second program parameter selected based on the severity of the memory hole mis-shape in the group.

Abstract: Non-volatile, high performance memory devices balance speed and reliability, which can include channel boosting to reduce data error rates in the memory cells. Vertical NAND strings exhibit greater program disturb (errors) the higher the wordline is on the string. The present disclosure applies a boosted bit line voltage or an increased precharge time when the programming reaches a level (wordline number) where it has been determined that errors due to program disturb may be an issue. The boost to the bit line may occur after a stored wordline value or based on a calculated number of errors at a previous wordline. In an example, the bit line stays the same as the prior world line programming operation until the likely program disturb is determined.

Abstract: A bandgap reference generation circuit in an integrated circuit (IC) and method for generating a bandgap reference voltage are disclosed. The bandgap reference generation circuit includes a first proportional to absolute temperature (PTAT) current generation section for generating a PTAT current component, a current circuit configured to generate a trimmed PTAT current component substantially invariant of sheet resistance of at least one resistor in the current circuit, and a complementary to absolute temperature (CTAT) current generation section including a diode on which the trimmed PTAT current component is fed to generate a CTAT current component. A combination of the PTAT and CTAT current components generate the bandgap reference voltage.

Abstract: Apparatuses and techniques are described for accessing redundant columns of data in a memory device. To facilitate scaling of a memory device and reduce a clock rate used to access latches of the redundant columns in program and read operations, one or more first-in, first out (FIFO) buffers are provided to output data to, and receive data from, the latches. The FIFO buffers act as an interface between a controller and the latches, and exchange data with the controller at a relatively high clock rate, and exchange data with the latches of the redundant columns at a slower clock rate. During a read operation, the FIFO can prefetch read data from one or more columns and store it until it is needed to replace the data of a defective primary column.

Abstract: An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.