Patents Assigned to SanDisk Technologies LLC
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Publication number: 20190245137Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.Type: ApplicationFiled: April 23, 2018Publication date: August 8, 2019Applicant: SanDisk Technologies LLCInventors: YOUNG-SUK CHOI, WON HO CHOI
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Publication number: 20190244673Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.Type: ApplicationFiled: June 25, 2018Publication date: August 8, 2019Applicant: SanDisk Technologies LLCInventors: XIANG YANG, DEEPANSHU DUTTA, HUAI-YUAN TSENG
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Patent number: 10374013Abstract: A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.Type: GrantFiled: March 30, 2017Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Abhijit Bandyopadhyay, Christopher J. Petti, Natalie Nguyen, Brian Le
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Patent number: 10372536Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.Type: GrantFiled: March 14, 2018Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
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Patent number: 10374148Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.Type: GrantFiled: April 23, 2018Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Young-Suk Choi, Won Ho Choi
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Patent number: 10373682Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.Type: GrantFiled: December 27, 2017Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Thomas Trent
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Patent number: 10372613Abstract: Systems, methods and/or devices are used to enable using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests including read requests and write requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including, for each sub-region of a plurality of sub-regions of the region: (a) determining whether the sub-region is accessed more than a predetermined threshold number of times during a predetermined time period, and (b) if so, caching, from a storage medium of the storage device to a cache of the storage device, data from the sub-region.Type: GrantFiled: July 3, 2014Date of Patent: August 6, 2019Assignee: Sandisk Technologies LLCInventors: Akshay Mathur, Dharani Kotte, Chayan Biswas, Baskaran Kannan, Sumant K. Patro
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Patent number: 10373697Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.Type: GrantFiled: February 15, 2018Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Chun-Hung Lai, Rajdeep Gautam, Ching-Huang Lu, Shih-Chung Lee
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Patent number: 10372529Abstract: A method is provided that includes performing first decoding operations on data obtained from a plurality of units of memory using soft information values for the plurality of units of memory, where the plurality of units of memory includes an error correction stripe. The method further includes determining that two or more units of memory have uncorrectable errors. The method further includes updating a soft information value for a first unit of memory in accordance with a magnitude of a soft information value for a second unit and a direction based on parity of the error correction stripe excluding the first unit, where the first unit of memory and the second unit of memory are included in the two or more units of memory that have uncorrectable errors. The method further includes performing a second decoding operation on data obtained from the first unit using the updated soft information value.Type: GrantFiled: December 17, 2015Date of Patent: August 6, 2019Assignee: Sandisk Technologies LLCInventors: Ying Yu Tai, Seungjune Jeon, Jiangli Zhu
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Patent number: 10374014Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: GrantFiled: January 12, 2018Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
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Publication number: 20190237470Abstract: A memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material.Type: ApplicationFiled: January 31, 2018Publication date: August 1, 2019Applicant: SanDisk Technologies LLCInventors: Teruyuki Mine, Christopher J. Petti
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Publication number: 20190235925Abstract: Data of a vector storage request pertaining to one or more disjoint, non-adjacent, and/or non-contiguous logical identifier ranges are stored contiguously within a log on a non-volatile storage medium. A request consolidation module modifies one or more sub-requests of the vector storage request in response to other, cached storage requests. Data of an atomic vector storage request may comprise persistent indicators, such as persistent metadata flags, to identify data pertaining to incomplete atomic storage requests. A restart recovery module identifies and excludes data of incomplete atomic operations.Type: ApplicationFiled: April 1, 2019Publication date: August 1, 2019Applicant: SanDisk Technologies LLCInventors: Ashish Batwara, James G. Peterson, Nisha Talagala, Nick Piggin, Michael Zappe
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Patent number: 10365841Abstract: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.Type: GrantFiled: July 13, 2015Date of Patent: July 30, 2019Assignee: SanDisk Technologies LLCInventors: Reuven Elhamias, Ram Fishler
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Patent number: 10367493Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.Type: GrantFiled: June 14, 2018Date of Patent: July 30, 2019Assignee: SanDisk Technologies LLCInventors: Sravanti Addepalli, Ravindra Arjun Madpur, Sridhar Yadala
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Patent number: 10366739Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. A voltage supply circuit may supply a selected pulse and an unselected pulse to the selected and unselected sense circuits. The selected sense circuits may pass the selected pulse to associated charge-storing circuits, and reject the unselected pulse. The unselected sense circuits may pass the unselected pulse to associated charge-storing circuits, and reject the selected pulse. In addition, voltage-setting circuitry may set sense voltages in the unselected sense circuits to a pre-sense level that matches the pre-sense level of communication voltages in the unselected sense circuits.Type: GrantFiled: June 20, 2017Date of Patent: July 30, 2019Assignee: SanDisk Technologies LLCInventors: Anirudh Amarnath, Tai-Yuan Tseng
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Patent number: 10366729Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.Type: GrantFiled: June 22, 2017Date of Patent: July 30, 2019Assignee: SanDisk Technologies LLCInventors: Tai-Yuan Tseng, Anirudh Amarnath
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Method and System for Visualizing a Correlation Between Host Commands and Storage System Performance
Publication number: 20190227735Abstract: A method and system for visualizing a correlation between host commands and storage system performance are provided. In one embodiment, a method comprises receiving information concerning host operations of a host performed over a time period; receiving information concerning storage system operations of a storage system performed over the time period; and simultaneously displaying both the host operations and the storage system operations over the time period. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: ApplicationFiled: April 1, 2019Publication date: July 25, 2019Applicant: SanDisk Technologies LLCInventors: Tal Shaked, Omer Gilad, Liat Hod, Eyal Sobol, Einav Zilberstein, Judah Gamliel Hahn -
Patent number: 10361690Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.Type: GrantFiled: June 14, 2018Date of Patent: July 23, 2019Assignee: SanDisk Technologies LLCInventors: Sravanti Addepalli, Ravindra Arjun Madpur, Sridhar Yadala
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Patent number: 10360045Abstract: A device or apparatus may be configured to perform memory operations on a memory die while a current multi-level cell programming operation is being performed. In the event that a controller identifies pending memory operations to be performed in the memory die, the controller may communicate with the memory die to determine a status of auxiliary latches of the memory die. Depending on the status, the controller may determine if the memory die is in a suspend/resume period and/or which pending memory operations to have performed.Type: GrantFiled: April 25, 2017Date of Patent: July 23, 2019Assignee: SanDisk Technologies LLCInventors: Uri Peltz, Amir Hadar, Mark Shlick, Mark Murin
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Publication number: 20190221274Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Applicant: SanDisk Technologies LLCInventor: Xiying Costa
