Patents Assigned to SanDisk Technologies LLC
-
Publication number: 20190115071Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: ApplicationFiled: January 12, 2018Publication date: April 18, 2019Applicant: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J. Petti, Gerrit Jan Hemink
-
Publication number: 20190115072Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: ApplicationFiled: January 12, 2018Publication date: April 18, 2019Applicant: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J. Petti, Gerrit Jan Hemink
-
Patent number: 10262730Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.Type: GrantFiled: January 12, 2018Date of Patent: April 16, 2019Assignee: SanDisk Technologies LLCInventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
-
Patent number: 10261695Abstract: Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. On method is implemented in a data storage device including a controller and a memory. The method includes collecting submission queue command statistics; monitoring resource state of the data storage device. The method further includes using the submission queue command statistics and the resource state to select a submission queue from which a next data storage device command should be fetched. The method further includes fetching the command from the selected submission queue. The method further includes providing the command to command processing logic.Type: GrantFiled: January 29, 2018Date of Patent: April 16, 2019Assignee: SanDisk Technologies LLCInventors: Shay Benisty, Noga Harari Shechter, Amir Segev, Tal Sharifie
-
Patent number: 10264097Abstract: A method and system for interactive aggregation and visualization of storage system operations are provided. In one embodiment, the method is performed by a server in communication with a client and comprises: receiving, from the client, data regarding storage system operations that were performed by a storage system over time, wherein each storage system operation is classified according to an operation type; receiving, from the client, a size of a graph to be displayed on the client's display device to visualize the storage device operations, wherein the size of the graph is defined by a number of tiles; for each tile, aggregating the storage system operations by operation type and identifying a dominant operation type; and sending, to the client, the identified dominant operation type for each tile. Other embodiments are provided.Type: GrantFiled: August 2, 2016Date of Patent: April 16, 2019Assignee: SanDisk Technologies LLCInventors: Tal Shaked, Omer Gilad, Liat Hod, Eyal Sobol
-
Patent number: 10262743Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.Type: GrantFiled: February 23, 2017Date of Patent: April 16, 2019Assignee: SanDisk Technologies LLCInventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
-
Publication number: 20190109585Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.Type: ApplicationFiled: January 19, 2018Publication date: April 11, 2019Applicant: SanDisk Technologies LLCInventors: Tianyu Tang, Venkatesh Ramachandra, Srinivas Rajendra
-
Publication number: 20190109584Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.Type: ApplicationFiled: January 19, 2018Publication date: April 11, 2019Applicant: SanDisk Technologies LLCInventors: Tianyu Tang, Venkatesh Ramachandra, Srinivas Rajendra
-
Publication number: 20190108883Abstract: A memory device and associated techniques for reducing disturbs of select gate transistors and dummy memory cells in a memory device. In one approach, a ramp up of the voltage of a dummy word line is delayed relative to a ramp up of a voltage of data word lines in a program phase of a program loop, after a pre-charge phase of the program loop. Another possible approach delays the ramp up of a first dummy memory cell while the voltage of a second dummy memory cell is maintained at an elevated level throughout the pre-charge phase and the program phase. In another aspect, the disturb countermeasure is used when the selected data memory cell is relatively close to the source-end of the memory string and phased out when the selected data memory cell is relatively close to the drain-end of the memory string.Type: ApplicationFiled: October 6, 2017Publication date: April 11, 2019Applicant: SanDisk Technologies LLCInventors: Xuehong Yu, Yingda Dong
-
Patent number: 10249382Abstract: Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.Type: GrantFiled: August 22, 2017Date of Patent: April 2, 2019Assignee: SanDisk Technologies LLCInventors: Dana Lee, Ekam Singh, Ashish Ghai, Kalpana Vakati
-
Patent number: 10250281Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.Type: GrantFiled: December 30, 2016Date of Patent: April 2, 2019Assignee: SanDisk Technologies LLCInventors: Stella Achtenberg, Omer Fainzilber, Ariel Navon, Alexander Bazarsky, Eran Sharon
-
Patent number: 10248587Abstract: Methods and systems are provided that execute reduced host data commands. A reduced host data command may be a write command that includes or is received with an indication of host data instead of the host data. The reduced host data command may be executed with a Direct Memory Access (DMA) circuit independently of a processor that executes administrative commands. In the execution of the reduced host data command, host data may be generated, metadata may be generated, and the generated host data and/or metadata may be copied into backend memory with the DMA circuit independently of the processor.Type: GrantFiled: November 8, 2013Date of Patent: April 2, 2019Assignee: SanDisk Technologies LLCInventors: Shay Benisty, Tal Sharifie, Girish Desai, Oded Karni
-
Patent number: 10249372Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.Type: GrantFiled: September 1, 2017Date of Patent: April 2, 2019Assignee: SanDisk Technologies LLCInventors: Hong-Yan Chen, Wei Zhao, Ching-Huang Lu, Yingda Dong
-
Patent number: 10249592Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.Type: GrantFiled: February 18, 2018Date of Patent: April 2, 2019Assignee: SanDisk Technologies LLCInventors: Michael Mostovoy, Gokul Kumar, Ning Ye, Hem Takiar, Venkatesh P. Ramachandra, Vinayak Ghatawade, Chih-Chin Liao
-
Patent number: 10241704Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.Type: GrantFiled: July 31, 2017Date of Patent: March 26, 2019Assignee: SanDisk Technologies LLCInventors: Daniel Tuers, Abhijeet Manohar, Jonathan Hsu
-
Patent number: 10242750Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.Type: GrantFiled: May 31, 2017Date of Patent: March 26, 2019Assignee: SanDisk Technologies LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Shantanu Gupta, Avinash Rajagiri, Dongxiang Liao, Jagdish Sabde, Rajan Paudel
-
Patent number: 10241938Abstract: Apparatuses, systems, and methods are disclosed for an output data path for non-volatile memory. A buffer may include a plurality of buffer stages. A buffer stage width may be a width of an internal bus for a non-volatile memory element. A buffer may include two or more read pointers, updated by an internal controller at different times in response to different portions of a clock signal. A parallel-in serial-out (PISO) component may receive data via an internal data path having a data path width equal to an internal bus width, and may output the data in a series of transfers controlled according to a clock signal, via an output bus having an output bus width narrower than an internal bus width. A PISO component may receive data from a portion of a buffer stage in response to an internal controller updating a read pointer to point to the buffer stage.Type: GrantFiled: December 20, 2017Date of Patent: March 26, 2019Assignee: SanDisk Technologies LLCInventors: Yukeun Sim, Yingchang Chen
-
Publication number: 20190088315Abstract: Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect, a non-volatile storage device has at least one monitor memory cell associated with a group of data memory cells. The non-volatile storage device may use different programming techniques to program the data and monitor memory cells. In one aspect, the programming technique used for the monitor memory cell is less stable with respect to state than the technique used to program the associated data memory cells. The state of the monitor memory cell may change in a predictable manner, such that the state of the monitor cell may be sensed periodically to determine whether the associated data memory cells should be refreshed.Type: ApplicationFiled: September 20, 2017Publication date: March 21, 2019Applicant: SanDisk Technologies LLCInventors: Juan Saenz, Christopher J. Petti
-
Publication number: 20190088335Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.Type: ApplicationFiled: March 30, 2018Publication date: March 21, 2019Applicant: SanDisk Technologies LLCInventors: Chia-Lin Hsiung, Fumiaki Toyama, Tai-Yuan Tseng, Yan Li
-
Patent number: 10235294Abstract: Apparatuses and techniques are described for performing a pre-read operation in preparation for a read operation in a memory device. The pre-read operation transitions the memory cells from a first read condition to a second read condition so that their threshold voltages will be in a desired, predictable range when the read occurs. The pre-read operation can involve maintaining voltages on a selected word line and unselected word lines at specified levels and for a specified duration which is relatively long compared to a duration of the read operation. The word line voltages, in combination with bit line and source line voltages, provide the channels of a NAND string in a conductive state and gradually transitions the memory cells to the second read condition.Type: GrantFiled: April 23, 2018Date of Patent: March 19, 2019Assignee: SanDisk Technologies LLCInventors: Ching-Huang Lu, Swaroop Kaza, Piyush Sagdeo
