Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.

Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element.

Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: Systems, apparatuses, and methods are provided that refresh data in a memory. Data is programmed into the memory. After which, part or all of the data may be refreshed. The refresh of the data may be different from the initial programming of the data in one or more respects. For example, the refresh of the data may include fewer steps than the programming of the data and may be performed without erasing a section of memory. Further, the refresh of the data may be triggered in one of several ways. For example, after programming the data, the data may be analyzed for errors. Based on the number of errors found, the data may be refreshed.

Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.

Abstract: Ring bus architectures for use in a memory module are disclosed. A memory module may include a primary ring bus; a ring bus controller positioned on the primary ring bus; a secondary ring bus in communication with the primary ring bus via a first bus bridge; and a tertiary ring bus in communication with the secondary ring bus via a second bus bridge. The ring bus controller is configured to direct the first bus bridge to route data between the primary ring bus and the secondary ring bus and is configured to direct the second bus bridge to route data between the secondary ring bus and the tertiary ring bus.

Abstract: A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. Core logic circuitry and data path circuitry may communicate pairs of phase-shifted data signals to the multiplexer. The multiplexer may use the clock signal and the pairs of phase-shifted data signals to generate an output pair of data signals, and send the output pair of data signals to the output driver circuitry. In turn, the output driver circuitry may generate an output data signal for communication on the communications bus. The clock-receiving system may enable the critical path and use the multiplexer to generate the output data signal when in a low operating voltage mode.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.

Abstract: An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

Abstract: Storage divisions are selected for garbage collection by use of a first selection criterion that is based on an amount of storage capacity freed by reclaiming the respective storage divisions. The first selection criterion may be overridden by a second, different selection criterion in response to determining that a wear variance of the storage divisions exceeds a threshold. The second selection criterion may select a storage division to reclaim based on a wear-level of the storage division. Overrides of the first selection criterion may be limited to a particular override frequency and/or period. The first selection criterion may comprise a logarithmic comparison of the amount of invalid data within the storage divisions. The amount of invalid data in a storage division may be calculated in terms of recovery blocks, having a size that exceeds the size of the physical storage locations within the storage divisions.

Abstract: The various implementations described herein include systems, methods and/or devices used for garbage collection in memory system. The method includes: (1) determining occurrences of triggering events including data reclamation events, urgent data integrity recycling events, and scheduled data integrity recycling events, and (2) recycling, in response to each of a plurality of triggering events, data in a predefined quantity of memory units from a source memory portion to a target memory portion of the memory system. A respective data reclamation event corresponds to the occurrence of host data write operations in accordance with a target reclamation to host write ratio. A respective urgent data integrity recycling event occurs when a memory portion satisfies predefined urgent read disturb criteria. A respective scheduled data integrity recycling event occurs at a rate corresponding to a projected quantity of memory units to be recycled by the memory system over a period of time.

Abstract: A storage system and method for reducing XOR recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. The controller is configured to generate a first exclusive-or (XOR) parity for pages of data written to the memory; after the first XOR parity has been generated, determine that there is at least one page of invalid data in the pages of data written to the memory; and generate a second XOR parity for the pages of data that excludes the at least one page of invalid data, wherein the second XOR parity is generated by performing an XOR operation using the first XOR parity and the at least one page of invalid data as inputs. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.

Abstract: Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to limit erase dwell times for blocks of a non-volatile memory medium to satisfy a threshold. A block classification module is configured to group blocks of a non-volatile memory medium based on retention times for the blocks. A block access module is configured to access at least one group of blocks using a read voltage threshold selected based on a grouping.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable hybrid microcontroller having a state machine and one or more processors. The state machine is configured to generate a first set of execution signals in response to a request to perform memory operations on non-volatile memory cells in the memory system. The first set of execution signals have a format configured to interface with one or more circuits coupled to the non-volatile memory cells. The hybrid microcontroller has an interface that translates the first set of execution signals to instruction identifiers. The one or more processors execute instructions identified by the instruction identifiers to generate a second set of execution signals. The second set of execution signals are provided to the one or more circuits to perform the memory operations on the non-volatile memory cells.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line.