Patents Assigned to SanDisk Technologies
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Patent number: 12205660Abstract: Techniques are provided for capturing a processing state snapshot of a device under test (DUT) that enable a previous test run to be restored and resumed from the same point the snapshot was taken. The techniques enable restoring the snapshot into the same or a different device to resume a previous test run. In an illustrative example, a DUT is controlled by a Joint Test Action Group (JTAG) test controller to capture a Steady State Snapshot by controlling peripheral components of the DUT to complete any on-going tasks to reach a steady state and then flush data to a memory of the DUT. The flushed steady state peripheral component data and other processing state data is transferred to the test controller for analysis and for enabling the subsequent restore and resume operation. Solid state drive (SSD) examples are provided.Type: GrantFiled: July 25, 2023Date of Patent: January 21, 2025Assignee: Sandisk Technologies, Inc.Inventors: Eran Moshe, Pavel Teper
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Patent number: 12205638Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.Type: GrantFiled: September 7, 2022Date of Patent: January 21, 2025Assignee: SanDisk Technologies LLCInventors: Nathan Franklin, Ward Parkinson, Michael Grobis, James O'Toole
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Patent number: 12205654Abstract: The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the bit lines during each of the three programming pulses. The patterns include two pre-established patterns and additional patterns that are derived from the pre-established patterns using logic operations.Type: GrantFiled: March 9, 2022Date of Patent: January 21, 2025Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Takayuki Inoue, Jiacen Guo
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Patent number: 12205640Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.Type: GrantFiled: July 14, 2021Date of Patent: January 21, 2025Assignee: SanDisk Technologies LLCInventors: Michael K. Grobis, Daniel Bedau, Christopher J. Petti
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Patent number: 12205008Abstract: A non-volatile memory device is configured for in-memory computation of layers of a neural network by storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element. By scaling the input voltages (representing inputs for the layer of the neural network) relative to the threshold values of the threshold switching selectors, dropout for inputs can be implemented to reduce overfitting by the neural network.Type: GrantFiled: May 13, 2021Date of Patent: January 21, 2025Assignee: SanDisk Technologies LLCInventors: Wen Ma, Tung Thanh Hoang, Martin Lueker-Boden
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Patent number: 12197323Abstract: In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is maintained that reflects an amount of memory written to by a host, as well as an amount of memory freed by garbage collection operations. Each step of a garbage collection operation can be performed in response to a value of the counter being greater than a threshold for the step such that there is a balance between memory written and memory freed.Type: GrantFiled: July 25, 2023Date of Patent: January 14, 2025Assignee: Sandisk Technologies, Inc.Inventors: Anamika Choudhary, Ramkumar Ramamurthy, Narendhiran Chinnaanangur Ravimohan, Lovish Singla, Meenakshi C, Bhagyashankar Muthu Kumaresan
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Patent number: 12197744Abstract: Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block. The control block may be a MasterIndexPage block. When a spare block is not available, the controller may erase information stored in an oldest debug memory block and copy data from the control block to the oldest debug memory block.Type: GrantFiled: August 10, 2023Date of Patent: January 14, 2025Assignee: Sandisk Technologies, Inc.Inventors: Maharudra Nagnath Swami, G K Divya, Naveen Menezes, Nitin Jain
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Patent number: 12197284Abstract: A read to a wordline can cause a read disturb error on neighboring wordlines. Instead of scanning the entire memory to identify wordlines that have a read disturb problem, a localized read scan approach can be used. In this approach, the memory is organized into several zones, where each zone contains several wordlines. The number of reads in each zone is tracked, and, after a certain number of reads, the data in the zone is read. If the error rate of the data exceeds a threshold, the data is relocated to another area of the memory.Type: GrantFiled: July 14, 2023Date of Patent: January 14, 2025Assignee: Sandisk Technologies, Inc.Inventors: Maharudra Nagnath Swami, Nitin Jain
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Patent number: 12197287Abstract: A data storage device includes a host interface for coupling the data storage device to a host system. The data storage device also includes a device memory for storing or providing data in response to commands receive from the host system. The data storage device also includes a controller comprising a storage subsystem and a security subsystem. The storage subsystem is configured to receive a host command from the host interface, and process the host command for the device memory. The security subsystem includes a device recovery circuit configured to monitor the storage subsystem for an exception state, and reinitialize pending operations for the storage subsystem after the exception state. Methods and systems are also disclosed.Type: GrantFiled: September 16, 2022Date of Patent: January 14, 2025Assignee: Sandisk Technologies, Inc.Inventors: Dattatreya Nayak, Rohit Prasad, Vinod Sasidharan
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Publication number: 20250010293Abstract: Methods of detecting molecules using an apparatus comprising a plurality of magnetic sensors are disclosed. A method may include binding a first molecule to a proximal wall of a fluid chamber of the apparatus, and adding, to the fluid chamber, a magnetically-labeled molecule comprising a cleavable magnetic label, wherein the magnetically-labeled molecule is configured to bind to or be incorporated by the first molecule. The method may use at least one address line and at least one selector element of the apparatus to detect a characteristic of at least a portion of the plurality of magnetic sensors, wherein the characteristic indicates whether the magnetically-labeled molecule has bound to or been incorporated by the first molecule.Type: ApplicationFiled: September 18, 2024Publication date: January 9, 2025Applicants: Roche Sequencing Solutions, Inc., Sandisk Technologies, Inc.Inventors: Yann ASTIER, Patrick BRAGANCA, Juraj TOPOLANCIK
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Patent number: 12189451Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.Type: GrantFiled: May 25, 2023Date of Patent: January 7, 2025Assignee: Sandisk Technologies, Inc.Inventors: Dmitry Vaysman, Eran Erez, Judah Gamliel Hahn, Sartaj Ajrawat
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Patent number: 12190969Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the planes in a smart verify operation. The control means concurrently programs at least some of the memory cells connected to each of the word lines in each of the planes in a program operation using the smart verify programming voltage individually acquired for each of the planes in the smart verify operation.Type: GrantFiled: August 25, 2022Date of Patent: January 7, 2025Assignee: SanDisk Technologies LLCInventors: Ke Zhang, Liang Li
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Patent number: 12189818Abstract: A data storage device and method for token generation and parameter anonymization are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a plurality of tokens and data comprising a plurality of data portions, which each token identifies a different set of the data portions to anonymize; create a plurality of anonymized versions of the data per the plurality of tokens; and store each of the plurality of anonymized versions of the data in different physical addresses in the memory, wherein the different physical addresses map to a same logical address in a mapping structure. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: May 4, 2022Date of Patent: January 7, 2025Assignee: Sandisk Technologies, Inc.Inventor: Ramanathan Muthiah
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Patent number: 12193166Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.Type: GrantFiled: April 13, 2022Date of Patent: January 7, 2025Assignee: Sandisk Technologies, Inc.Inventors: Songtao Lu, Hsiang Ju Huang, Binbin Zheng, Cheng-Hsiung Yang, Chien-Te Chen
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Publication number: 20250004660Abstract: A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.Type: ApplicationFiled: August 3, 2023Publication date: January 2, 2025Applicant: Sandisk Technologies, Inc.Inventors: Daniel J. Linnen, Ramanathan Muthiah, Preston Thomson, Kirubakaran Periyannan, Niles Nian Yang, Inez Hua, Judah Gamliel Hahn
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Patent number: 12182439Abstract: A data storage device includes a memory device and a controller to the memory device. The controller is configured to receive key value (KV) pair data having a key and a value from a host device and generate a mapping in a key-to-physical (K2P) table corresponding to the received KV pair data. The mapping includes a first slot for storing a physical address corresponding to the value and a second slot for storing a physical address corresponding to metadata associated with the KV pair data. When the associated metadata is sent to the data storage device, which may be non-concurrent to transferring the KV pair data, the mapping of the associated metadata is linked to a same key as the mapping of the KV pair data. Thus, using the mapping, the key of the KV pair data is associated with the KV pair data and the associated metadata.Type: GrantFiled: September 6, 2022Date of Patent: December 31, 2024Assignee: Sandisk Technologies, Inc.Inventor: Ramanathan Muthiah
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Patent number: 12182454Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to maintain a plurality of virtual pools, wherein each virtual pool corresponds with an logical block address (LBA) range, update a counter of a virtual pool, wherein the counter corresponds to a health of the LBA range, and select, based on the counter, the virtual pool to program data to. The controller is further configured to maintain a counter for each application having data programmed to the virtual pool, where the counter is increased for each write operation to the virtual pool. When the counter equals or exceeds a threshold value, the controller is configured to send a warning to each application associated with the virtual pool having the counter that equals or exceeds the threshold value.Type: GrantFiled: March 20, 2023Date of Patent: December 31, 2024Assignee: Sandisk Technologies, Inc.Inventors: Rotem Sela, Asher Druck
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Patent number: 12182430Abstract: Certain aspects of the present disclosure provide techniques for proving possession of data in a storage device participating in a distributed data storage network. An example storage device includes a storage circuitry and a trusted circuit. The storage circuitry is configured to store a plurality of data blocks. The trusted circuit generally has a private signing key securely stored thereon. The trusted circuit is generally configured to compute a hash over data stored in a plurality of data blocks and to generate an anonymous digital signature for the data stored in the plurality of data blocks based at least in part on the private signing key and the computed hash. The trusted circuit may be interposed on a write path to the storage circuitry such that data written to the storage circuitry is processed through the trusted circuit.Type: GrantFiled: November 29, 2021Date of Patent: December 31, 2024Assignee: Sandisk Technologies, Inc.Inventors: Shashank Agrawal, Cyril Guyot
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Patent number: 12182451Abstract: The present disclosure generally relates to improved fragment processing while command fetching is on-going. Rather than stopping command fetching, the controller uses a short fragment list, while command fetching can continue, to add a fragment. The controller first adds new fragments to the short list with the fragment information. The information is then checked for size. If the fragment information is smaller than the short fragment list, then the fragment list is updated during command fetching. As a command arrives, the controller does a binary search of a sorted fragment list. The results are stored and later scanned by the controller for matches with the short fragment list. If there are no matches in the short list, then the controller uses the stored results to update the search result. If there is a match in the short list then the controller uses the new results to update the search list.Type: GrantFiled: July 19, 2023Date of Patent: December 31, 2024Assignee: Sandisk Technologies, Inc.Inventors: Amir Segev, Shay Benisty
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Patent number: 12183386Abstract: The present disclosure generally relates to aligning non-aligned data for more efficient data reading. Data for write commands does not always perfectly align, yet the data is written in order of write command receipt. In such cases, aligned chunks of data may be split into two word lines (WLs) due to the presence of previously received smaller chunks of data. Rather than writing the data in order, the smaller chunks of data, which are non-aligned, are held in a buffer and written later to ensure that any aligned chunks of data remain aligned when written to the memory device. Once sufficient smaller chunks or data have accumulated to be aligned, or upon a need to write the smaller chunks upon reaching a threshold, the smaller chunks are written together in a single WL so as to not cause non-alignment of aligned data.Type: GrantFiled: September 6, 2022Date of Patent: December 31, 2024Assignee: Sandisk Technologies, Inc.Inventors: Alexander Bazarsky, Judah Gamliel Hahn, Michael Ionin
