Patents Assigned to Sanyo Semiconductor Co., Ltd.
  • Patent number: 8482182
    Abstract: A driving apparatus includes a piezoelectric element which undergoes expansion/contraction motion by a driving signal; a driving shaft which is mounted on the piezoelectric element, and undergoes reciprocating movement according to the expansion/contraction motion of the piezoelectric element; a first movement member which is friction-engaged with the driving shaft, and moves due to the reciprocating movement of the driving shaft; and a first control portion which applies driving signals to the piezoelectric element; the first control portion applies driving control pulse signals when the first movement member is to be moved, and applies stop control pulse signals when the stopped first movement member is not to be moved to put the first movement member into a vibration-arrested state. By this means, the stopped first movement member can be smoothly moved, and the first movement member in motion can be smoothly stopped.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: July 9, 2013
    Assignees: FUJIFILM Corporation, Sanyo Semiconductor Co., Ltd., Sanyo Electric Co., Ltd.
    Inventors: Hisao Ito, Hideo Yoshida, Takezo Nagamitsu, Tetsuya Tokoro, Yukihiko Sigeoka
  • Patent number: 8467544
    Abstract: A filter coefficient setting device for setting a filter coefficient of an echo prevention device including a first FIR filter, and a second FIR filter, comprises: a filter coefficient initial setting portion configured to set a predetermined filter coefficient for the first and second FIR filters when the echo prevention device is started.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: June 18, 2013
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Takeo Inoue, Hideki Ohashi
  • Patent number: 8461663
    Abstract: In a conventional semiconductor device, part of a dielectric film of a capacitive element is removed when photoresist is peeled off, and this causes problems of variation in capacitance value of the capacitive element and deterioration of breakdown voltage characteristics. In a semiconductor device according to the present invention, a silicon nitride film serving as a dielectric film is formed on the top face of a lower electrode of a capacitive element, and an upper electrode is formed on the top face of the silicon nitride film. The upper electrode is formed of a laminated structure having a silicon film and a polysilicon film protecting the silicon nitride film. This structure prevents part of the silicon nitride film from being removed when, for example, photoresist is peeled off, thereby preventing variation in capacitance value of the capacitive element and deterioration of the breakdown voltage characteristics.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: June 11, 2013
    Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Reiki Fujimori, Mitsuru Soma
  • Patent number: 8461796
    Abstract: A coil current detector detects a current component flowing through a coil. A scaling unit scales a drive signal. An induced voltage component extraction unit extracts an induced voltage component by removing the drive signal, scaled by the scaling unit, from the coil current component detected by the current detector. A phase difference detector detects a phase difference between the phase of the drive signal and that of the induced voltage component. A signal adjustment unit adjusts the drive signal so that the phase difference detected by the phase difference detector can be brought close to a target phase difference.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: June 11, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Kazumasa Takai
  • Patent number: 8452234
    Abstract: A communication system is provided comprising a living body-side electrode which primarily capacitively couples with a living body, an environment-side electrode which primarily capacitively couples with an external environment, and a circuit board on which a circuit which processes a signal which is output from at least one of the living body-side electrode and the environment-side electrode is mounted, wherein the circuit board is not placed between the living body-side electrode and the environment-side electrode.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: May 28, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Kazuo Hasegawa, Hirohisa Suzuki
  • Patent number: 8451337
    Abstract: An image stabilization control circuit controls an optical element driving element that moves an optical element provided in an imaging apparatus based on an output signal of a vibration detection element provided in the imaging apparatus. The image stabilization control circuit includes a high-pass filter that removes a low-frequency component from an output signal of the vibration detection element. A movement amount calculation circuit calculates a movement amount of the imaging apparatus based on an output signal of the high-pass filter. A servo circuit generates a correction signal for correcting the position of the optical element based on an output signal of the movement amount calculation circuit and outputs the correction signal to the optical element driving element. The movement amount calculation circuit includes a digital filter circuit and a register. The digital filter circuit performs filter processing based on a filter coefficient stored in the register.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 28, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Hideki Hirayama
  • Patent number: 8451373
    Abstract: An input unit writes, into a memory unit, frames successively input from the outside. An interpolated frame generating unit reads multiple original frames from the memory unit, generates an interpolated frame between the original frames, and writes the interpolated frame into the memory unit. An output unit retrieves original frames and an interpolated frame from the memory unit and outputs to the outside the frames in the order in which the frames are to be displayed. The input unit, interpolated frame generating unit, and output unit operate in parallel to perform pipeline processing. Operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: May 28, 2013
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Riichi Furukawa, Satoshi Otowa
  • Patent number: 8447251
    Abstract: An audio signal processing circuit comprising: a modulation circuit configured to output a modulated signal of a frequency corresponding to an input audio signal; a drive circuit configured to generate a driving current for driving the modulation circuit based on a control signal; an audio detection circuit configured to detect presence or absence of the audio signal input to the modulation circuit; and a control signal generation circuit configured to generate the control signal for generating the driving current in the drive circuit when the presence of the audio signal is detected and generate the control signal for stopping generation of the driving current in the drive circuit when the absence of the audio signal is detected for a predetermined period, based on a detection result of the audio detection circuit.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 21, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Toru Odajima, Masahiro Obuchi
  • Patent number: 8441462
    Abstract: This invention offers a signal processing circuit of an electrostatic capacity type touch panel which is capable of switching between a differential input mode and a single input mode and has an extended adjustable range of an offset in the single input mode. The signal processing circuit of this invention includes a first sensor circuit of a differential input type, a second sensor circuit of a single input type, a third and fourth electrostatic capacitors that are variable capacitors for calibration to adjust the offset in an output voltage of the first sensor circuit, and a switching control circuit to control so as to put in operation one of the first and second sensor circuits. The switching control circuit also controls so that the third and fourth electrostatic capacitors for calibration are connected in parallel to each other when the second sensor circuit is put in operation.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 14, 2013
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Kazuyuki Kobayashi, Yasuhiro Kaneta
  • Patent number: 8436250
    Abstract: A circuit device of the present invention includes a wiring board 45, and circuit elements such as semiconductor elements 32 mounted on the wiring board 45. The wiring board 45 includes: a conductive pattern 12, which is a metal core layer; a first insulating layer 14 and a second insulating layer 16 respectively covering an upper surface and a lower surface of the conductive pattern 12; and a first wiring layer 18 and a second wiring layer 20 formed respectively on an upper surface of the first insulating layer 14 and a lower surface of the second insulating layer 16. The conductive pattern 12 is made of rolled metal. With this configuration, the thermal resistance of the conductive pattern 12, which is the metal core, is reduced, and the thermal dissipation of the entire device can be improved.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: May 7, 2013
    Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Kouji Takahashi, Yusuke Igarashi, Jun Sakano
  • Patent number: 8431998
    Abstract: A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: April 30, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Takuji Miyata
  • Patent number: 8427804
    Abstract: A power amplifier for driving a load connected to an output terminal having an output transistor connected in parallel with a corresponding current detection path between the output terminal and a power supply. The detection path includes a switching device and a resistor connected in series, the switching device is turned on only during an on-state period of the corresponding output transistor, and the presence or absence of over-current generation is detected at the output transistors on the basis of a sensing signal obtained from a point connecting the switching device and the resistor. When over-current is detected, the operation of the output transistors is stopped to protect the amplifier.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: April 23, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Yoshitaka Matsumoto
  • Patent number: 8426944
    Abstract: In some embodiments, an insulated gate bipolar transistor includes a drift layer, insulation gates formed at a principle surface portion of the drift layer, base regions formed in a between-gate region, an emitter region formed in the base region so as to be adjacent to the insulation gate, an emitter electrode connected to the emitter region, a collector layer formed at the other side of the principle surface portion of the drift layer, and a collector electrode connected to the collector layer. The conductive type base regions are separated with each other by the drift layers, and the drift layer and the emitter electrode are insulated by an interlayer insulation film.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 23, 2013
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Shuji Yoneda, Kenji Sawamura
  • Patent number: 8415932
    Abstract: A switching control circuit includes an N-channel MOSFET having an input electrode applied with an input voltage and an output electrode connected to one end of an inductor and one end of a rectifying element. The other end of the inductor is connected to a first capacitor. A bootstrap circuit is configured to generate a bootstrap voltage on a second capacitor having one end connected to the output electrode of the N-channel MOSFET. The bootstrap voltage is required when the N-channel MOSFET is turned on. A driving circuit is configured to be applied with a driving voltage corresponding to the bootstrap voltage and turn on/off the N-channel MOSFET to generate an output voltage of a target level on the first capacitor. A clamping circuit is configured to clamp the driving voltage to be at a predetermined level or lower.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 9, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Yosuke Kobayashi, Iwao Fukushi
  • Patent number: 8411202
    Abstract: In an automatic gain control circuit comprising a black level detecting unit which detects a black level from a video signal, a white level detecting unit which detects a white level from the video signal, and an analog-to-digital converter which adjusts a dynamic range of the video signal based on a difference value between the black level and the white level, a video signal for adjustment including a black level which indicates a minimum brightness of a video image and a white level which indicates a maximum brightness of the video image is input and the dynamic range is adjusted.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: April 2, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC.
    Inventors: Hirotoshi Mori, Hiroyuki Ebinuma
  • Patent number: 8410577
    Abstract: The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: April 2, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsu Horikoshi, Hisayoshi Uchiyama, Takashi Noma, Yoshinori Seki, Hiroshi Yamada, Shinzo Ishibe, Hiroyuki Shinogi
  • Patent number: 8410537
    Abstract: The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: April 2, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Takashi Hiroshima
  • Patent number: 8400516
    Abstract: A image stabilization control circuit is provided that comprises at least one analog-to-digital converter circuit that converts an output signal of a vibration detection element which detects vibration of an imaging device, and an output signal of a position detection element which detects a position of an optical component or an imaging element, into digital signals, and a logic circuit that generates a control signal which drives the optical component or the imaging element, based on the output signal of the vibration detection element which is digitized by the analog-to-digital converter circuit and the output signal of the position detection element which is digitized by the analog-to-digital converter circuit, wherein an offset value and an amplitude for the output signal of the position detection element are adjusted.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 19, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Yasuhisa Yamada, Yuuki Tashita
  • Patent number: 8400097
    Abstract: The effect of chattering on the measurement of the pulse period is reduced. The pulse period representing the rise interval of target pulses appearing in a pulse signal PI is measured. The pulse signal PI is sampled in synchronization with a measurement clock CLK. Measurement of a designated inhibition period is started in synchronization with the fall of the signal PI. Measurement of the current pulse period is completed and measurement of a new pulse period is started if the inhibition period has elapsed at the rise of the signal PI. Counting of the current pulse period is continued if the inhibition period has not elapsed.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: March 19, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Kazumasa Takai
  • Patent number: 8395210
    Abstract: The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A?. A first body layer 17A? is formed by this first ion implantation. The first body layer 17A? is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A? in the first corner portion 14C1 is higher than that of a conventional transistor.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: March 12, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake, Shuichi Kikuchi