Patents Assigned to Sanyo Semiconductor Co., Ltd.
  • Patent number: 8237241
    Abstract: A conventional semiconductor device has a problem that an on-current of a parasitic transistor flows through a surface portion of a semiconductor layer and thus a semiconductor element undergoes thermal breakdown. In a semiconductor device according to the present invention, a protection element is formed with use of an isolation region and N type buried layers. A PN junction region in the protection element is formed on a P type buried layer of the isolation region. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of a semiconductor element to be protected. This structure allows an on-current of a parasitic transistor to flow into the protection element, and thereby the semiconductor element is protected. In addition, the on-current of the parasitic transistor flows through a deep portion of the epitaxial layer, and thereby the protection element is prevented from thermal breakdown.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: August 7, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Seiji Otake
  • Patent number: 8229288
    Abstract: A stream data reproducing system comprising: an input buffer configured to accumulate stream data input from a stream source; a decode circuit configured to decode the stream data accumulated in the input buffer by predetermined processing unit to generate decode data; an output buffer configured to output the decode data after accumulation thereof; a transfer memory cell configured to store the stream data accumulated in the input buffer and the decode data generated in the decode core circuit; and a data transfer control circuit configured to control transfer of the stream data by the processing unit from the input buffer to the transfer memory cell, and transfer of the decode data by the processing unit from the transfer memory cell to the output buffer.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: July 24, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventor: Kazuhiro Nakamuta
  • Patent number: 8227901
    Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: July 24, 2012
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsuyuki Seki, Akira Suzuki, Keita Odajima, Kikuo Okada, Koujiro Kameyama
  • Patent number: 8227341
    Abstract: An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 24, 2012
    Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd.
    Inventors: Satoshi Onai, Minoru Akaishi, Hiroshi Ishizeki, Yoshiaki Sano
  • Patent number: 8223058
    Abstract: A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: July 17, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Shigeto Kobayashi, Atsushi Wada, Toru Dan
  • Patent number: 8224245
    Abstract: The IC card is mounted on the read and write device and the first electrostatic induction electrode and second electrostatic induction electrode are formed facing each other. The data signal is outputted from the first transmission and reception circuit to the first electrostatic induction electrode when the data signal is transmitted from the IC card to the read and write device. Then the first electrostatic induction electrode is charged based on the data signal and the electrostatic induction signal of the opposite polarity is induced at the second electrostatic induction electrode. The inverted data signal appears at the second electrostatic induction electrode. The second transmission and reception circuit of the read and write device receives and amplifies the inverted data signal, leading to the non-contact data communication with lower energy consumption and the lower cost.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: July 17, 2012
    Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd.
    Inventor: Hideo Kondo
  • Patent number: 8217486
    Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: July 10, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Hiroyasu Ishida, Yasuyuki Sayama
  • Patent number: 8217714
    Abstract: A power consumption of a light-receiving device is reduced while a power consumption of a microcomputer that controls the light-receiving device is reduced as well. The microcomputer is structured to include a drive circuit, a sampling/detection circuit, a timer, a system clock generation circuit, a CPU, a ROM and a RAM. The CPU stops providing the light-receiving device with a power supply by turning off a P channel type MOS transistor with the drive circuit and sets the microcomputer in a standby state for a predetermined period of time. When the microcomputer is released from the standby state, the CPU starts providing the light receiving device with the power supply by turning the P channel type MOS transistor on with the drive circuit.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: July 10, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Hideo Kondo
  • Patent number: 8212925
    Abstract: A sync separation circuit separates a synchronizing signal from a video signal containing the synchronizing signal. A minimum level detecting section detects a minimum level of a video signal. A sync tip level detecting section detects a sync tip level in the video signal. A pedestal level detecting section detects a pedestal level in the video signal. Based on both the sync tip level detected by the sync tip level detecting section and the pedestal level control by the pedestal level detecting section, a slice level setting section sets a slice level corresponding to an intermediate value between the sync tip level and the pedestal level. The slice level control section sets the slice level based on the minimum level detected by the minimum level detecting section if the slice level set based on the sync tip level and the pedestal level is inappropriate.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: July 3, 2012
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Toru Okada, Hiroyuki Ebinuma
  • Patent number: 8203524
    Abstract: A light-emitting element driving circuit (10) comprises a luminosity determining unit (70) which determines luminosity, outputs a luminosity determination result, and outputs brightness change information, a brightness setting unit (60) which outputs brightness setting information and outputs brightness change information, a light-emitting element driving unit (40) which drives a light-emitting element with a current of a current value corresponding to the brightness setting information, a detecting and comparing unit (50) which compares a terminal voltage of the light-emitting element and a predetermined voltage, a voltage boost determining unit (30) which determines whether or not a terminal voltage of the light-emitting element is to be boosted based on at least one of the luminosity change information and the brightness change information, and a voltage boosting circuit section (20) which boosts the terminal voltage of the light-emitting element when it is determined that the voltage is to be boosted and
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: June 19, 2012
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Tomoshi Yoshida, Nobuyuki Ohtaka
  • Patent number: 8199206
    Abstract: In an image stabilization control circuit for an image capturing device, a gyro-equalizer (24) is used to integrate an angular velocity signal corresponding to vibration, and determine a required magnitude of lens displacement. The gyro-equalizer (24) integrates the angular velocity signal from a gyro-sensor (12) using an integration circuit (46) (LPF), and converts the signal into an angular signal. A direct current component of the angular signal is removed using a centering circuit (50) (HPF). The LPF and HPF can produce an insufficient phase delay in a low-band side of a target compensation region. A phase lag compensation circuit (48) comprising a low-boost filter compensates for the insufficient phase delay, and brings the phase delay of the angular signal with respect to the angular velocity signal close to 90° in an integration process.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: June 12, 2012
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Yoshihisa Tabuchi
  • Patent number: 8193084
    Abstract: When a bump electrode is formed on an opening formed in a semiconductor substrate, the invention prevents a void that is caused by gas trapped in the opening. A method of manufacturing a semiconductor device of the invention includes forming a first wiring on a main surface of a semiconductor substrate, forming an opening in the semiconductor substrate from the back surface to the main surface so as to expose the back surface of the first wiring, forming a second wiring connected to the back surface of the first wiring and extending from inside the opening onto the back surface of the semiconductor substrate, forming a solder layer connected to part of the second wiring on the bottom of the opening and extending from inside the opening onto the back surface of the semiconductor substrate, and forming a bump electrode on the opening by reflowing the solder layer.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: June 5, 2012
    Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Kazuyuki Sutou, Hiroaki Tomita
  • Patent number: 8188497
    Abstract: The invention is directed to providing a smaller semiconductor device with a lower manufacturing cost and higher reliability and a method of manufacturing the same. A light emitting element (a LED die 8) is formed on a first substrate 1. A cathode electrode 10 connected to an N type region of the LED die 8 is formed between the first substrate 1 and the LED die 8. The side surface of the LED die 8 is covered by an insulation layer 11. An anode electrode 12 is formed extending from on the front surface of the first substrate 1 onto a P type region of the LED die 8 along the circumference of the insulation layer 11. Wiring layers 18 electrically connected to the cathode electrode 10 and the anode electrode 12 are formed on the side surface of the first substrate 1 therealong. The wiring layers 18 extend onto the back surface of the first substrate 1.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: May 29, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Takashi Noma
  • Patent number: 8187949
    Abstract: When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form groove portions 4 therein, and in this state, the front surface of the wafer 2a is attached to a supporting body 5 having rigidity with an adhesive layer 6. Then, the wafer 2a is ground from the back surface and diced into individual dies 2b, and then a back surface process including a heat treatment such as the formation of back surface electrodes 9a is performed in the state where the dies 2b are attached to the supporting body 5.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: May 29, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Koujiro Kameyama
  • Patent number: 8190014
    Abstract: A focus control circuit is installed in an image pickup apparatus including a lens, a driver element for adjusting the position of the lens, and a position detecting element for detecting the position of the lens. A feedback equalizer included in the focus control circuit generates a drive signal used to adjust the position of the lens to a target position, based on a difference between the position of the lens identified by the output signal of the position detecting element and the target position of the lens set externally, and controls the driver element.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: May 29, 2012
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Hiroyuki Tsuda, Takeshi Kura
  • Patent number: 8179107
    Abstract: A power supply circuit comprising: a voltage generating circuit configured to generate an output voltage of a target level from an input voltage; an overcurrent protection circuit configured to control the voltage generating circuit so as to stop an output current, when a level of the output current generated at a time of generating the output voltage is greater than a reference level; and a reference-level change circuit configured to change the reference level in the overcurrent protection circuit to be at a second level higher than a first level from the first level for a predetermined period, when the overcurrent protection circuit detects that the level of the output current is greater than the reference level.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: May 15, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventor: Iwao Fukushi
  • Patent number: 8179075
    Abstract: A motor driving integrated circuit comprising: a speed control circuit configured to control a rotation speed of a motor according to a speed control signal; a detecting circuit configured to detect whether the speed control signal indicates stop of rotation of the motor; and a shut-off circuit configured to shut off power supply to a circuit included in the motor driving integrated circuit when the detecting circuit detects that the speed control signal indicates stop of rotation of the motor.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 15, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Hidemi Maeto, Shunji Suzuki
  • Patent number: 8180070
    Abstract: A howling suppressing apparatus includes: a detecting unit configured to detect howling of input audio signals; a plurality of filters configured to apply a filter process sequentially to the audio signals to be output; and a setting unit configured to set a filter coefficient for suppressing the howling detected by the detecting unit for a filter among the plurality of filters, in which filter no filter coefficient for suppressing howling is set, and set a filter coefficient for suppressing the howling detected by the detecting unit for any one of the plurality of filters, if filter coefficients for suppressing howling are set in all of the plurality of filters, based on the detection result from the detecting unit.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 15, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventor: Hirotaka Tatsumi
  • Patent number: 8179088
    Abstract: A noncontact transmission device 100 is provided with a driver 106 for driving a coil 102; a system clock oscillator 110 for outputting a system clock; a monitoring clock oscillator 112 for outputting a monitoring clock LF0 having a frequency lower than that of the system clock CK0; and a control circuit 108. The control circuit 108 outputs a system clock oscillating control signal S60 based on the monitoring clock LF0 while being in a standby state and makes the system clock oscillator 110 intermittently output a system clock CK0 in synchronization with the control signal S60. In a period when the system clock CK0 is being outputted, the coil 102 is driven by a driver control signal SD and whether the device 200 to which data is to be transmitted is arranged or not is detected.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: May 15, 2012
    Assignees: Aska Electron Corporation, Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Konomu Takaishi, Kazunori Nohara
  • Patent number: 8173543
    Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: May 8, 2012
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsuyuki Seki, Akira Suzuki, Koujiro Kameyama, Takahiro Oikawa