Patents Assigned to Scintera Networks
  • Patent number: 7039104
    Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 2, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian
  • Patent number: 7035330
    Abstract: A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit M. Phanse, Jishnu Bhatacharjee, Debanjan Mukherjee, Venugopal Balasubramonian, Fabian Giroud, Edem Ibragimov
  • Patent number: 7031383
    Abstract: A compensation circuit for reducing intersymbol interference (ISI) products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium provides for selective application of compensation to individual, discrete data signal components. According to one embodiment, one circuit branch processes the electrical data signal to substantially remove one distinct signal component representing an ISI product of some portion of the data symbol sequence. A second circuit branch approximately duplicates an ISI product of another portion of the data symbol sequence for removal by subtraction within a signal combiner from the compensated signal provided by the first circuit branch. A third circuit branch approximately duplicates an ISI product of still another portion of the data symbol sequence also for removal by subtraction within the signal combiner from the compensated signal provided by the first circuit branch.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: April 18, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Patent number: 7026873
    Abstract: Systems and methods are disclosed to adaptively pre-distort a signal prior to being used by a non-linear circuit, such as a higher power amplifier (at transmit) or a low noise amplifier (at receive). The signal is compared with a feedback signal from the non-linear circuit and a metric is calculated and minimized. The input signal is adaptively changed, such as by varying tap coefficients, until the metric is sufficiently minimized, resulting in a pre-distorted signal that is substantially linear upon passing through the non-linear circuit.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: April 11, 2006
    Assignee: Scintera Networks
    Inventor: Abhijit G. Shanbhag
  • Patent number: 7020402
    Abstract: A crosstalk compensation engine for reducing signal crosstalk effects within a data signal. Demultiplexed data signals corresponding to multiplexed data signals received via a signal transmission medium are processed to significantly reduce one or more signal crosstalk products related to one or more interactions among the multiplexed data signals within the signal transmission medium. Such signal crosstalk products include those resulting from dense wavelength-division mutiplexing of the data signals used to provide the multiplexed data signals, four-wave mixing among the multiplexed data signals within the signal transmission medium, and cross-phase modulation among the multiplexed data signals within the signal transmission medium.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: March 28, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Patent number: 7016406
    Abstract: Tap coefficients for fractionally-spaced equalizers are updated iteratively using error statistics from an input bit stream and an output bit stream, such as from a forward error correction circuit. The process continues until the errors converge to a sufficiently small number. Knowledge of the error patterns are used apriori to adaptively change the tap coefficients in a feedforward filter.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: March 21, 2006
    Assignee: Scintera Networks
    Inventors: Abhijit Phanse, Abhijit G. Shanbhag, Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Prashant Choudhary, Debanjan Mukherjee, Fabian Giroud, Edem Ibragimov
  • Patent number: 7005920
    Abstract: A programmable passive inductor includes two inductors or coils, each having a self-inductance, magnetically coupled together and having a mutual inductance proportional to a magnetic coupling factor. The relative magnitude of the currents through the two inductors can be dynamically varied, which changes the effective inductance.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: February 28, 2006
    Assignee: Scintera Network
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee
  • Patent number: 6985036
    Abstract: A digitally controlled transconductance cell includes a differential transistor pair coupled to load elements (either passive or active with resistive or impedance loads) and a variable bias current source, where the transconductance or gain is digitally varied by changing the aspect ratio of the transistors and the bias current.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: January 10, 2006
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Publication number: 20050271138
    Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
    Type: Application
    Filed: July 21, 2005
    Publication date: December 8, 2005
    Applicant: Scintera Networks, Inc.
    Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit Shanbhag, Edem Ibragimov, Fabian Giroud
  • Patent number: 6965337
    Abstract: Systems and methods are disclosed herein to provide reference generators. For example, in accordance with an embodiment of the present invention, a reference generator is provided for an electrical device, such as for example for an analog-to-digital converter. The reference generator may provide one or more reference signals having a common mode voltage that can track or be varied based on a common mode voltage of an input signal. Alternatively or in addition, the reference generator may provide reference signals for single-ended applications.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: November 15, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud
  • Patent number: 6952132
    Abstract: Systems and methods provide automatic gain control, such as by employing analog and digital techniques. For example, overall gain may be controlled through coarse and fine control signals provided to gain stages, with the overall gain monitored via a power detector circuit.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: October 4, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Patent number: 6940352
    Abstract: A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0?r?1 and such that a second input voltage may be multiplied by the complement factor (1?r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 6, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Patent number: 6940386
    Abstract: An integrated circuit including a differentially excited symmetric microstrip inductor formed over multiple layers while maintaining both electrical and geometrical symmetry.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 6, 2005
    Assignee: Scintera Networks, Inc
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Abhijit Phanse
  • Patent number: 6940898
    Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: September 6, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian
  • Publication number: 20050190832
    Abstract: A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 1, 2005
    Applicant: Scintera Networks, Inc.
    Inventors: Edem Ibragimov, Qian Yu, Prashant Choudhary
  • Patent number: 6922440
    Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 26, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Edem Ibragimov