Abstract: An apparatus, system, and method for a Gigasonic Brush for cleaning surfaces is presented. One embodiment of the system includes an array of acoustic transducers coupled to a substrate where the individual acoustic transducers have sizes in the range of 9 um2 to 250,000 um2. The system may include a positioning mechanism coupled to at least one of a target surface or the array of acoustic transducers, and configured to position the array of acoustic transducers within 1 millimeter of a target surface. The system may also include a cleaning liquid supply arranged to provide cleaning liquid for coupling the array of acoustic transducers to the target surface. The system may further include a controller coupled to the array of acoustic transducers and configured to activate the array of acoustic transducers.

Abstract: The present invention includes methods directed to improved processes for producing a monolayer of sulfur on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element.

Abstract: Embodiments of the present disclosure relate to methods and apparatus for reduction of particle defects from a semiconductor surface, such as for example the reduction of sub 100 micron defects. Methods and apparatus of the present disclosure are particularly useful in the manufacture of semiconductor devices when employing extreme ultraviolet photolithography. In some embodiments, a fluid stream is provided through a nozzle at conditions such that cavitation bubbles are formed, the cavitation bubbles being present in a stable cavitation state or regime. The fluid stream is flowed over at least a portion of the surface. A shockwave is generated or created in the fluid stream. The shockwave momentarily increases acoustic pressure in the fluid causing the cavitation bubbles to collapse and produce a jet or pulse of high fluid flow which removes particle defects from the surface.

Abstract: A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer.

Abstract: Systems and methods are provided facilitating a steaming fluid flow utilizing acoustic waves. A system includes an acoustic wave generator and an acoustic coupler associated with the acoustic wave generator and coupling acoustic waves generated by the acoustic wave generator into a fluid. The acoustic coupler includes one or more acoustic coupling lenses, which direct the acoustic waves into the fluid and facilitate, at least in part, a streaming fluid flow in a common direction. In an enhanced embodiment, the common flow direction is at an angle to a direction acoustic waves are generated, and the acoustic coupling lens(es), in directing the acoustic waves into the fluid, redirects the acoustic waves from the direction of acoustic wave generation. The acoustic wave generator generates the acoustic waves in the megahertz or gigahertz range, for example, with a frequency of 20 MHz or higher.

Abstract: A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via.

Abstract: A heterogeneous stack structure is provided which includes one or more optical signal-based chips and multiple electrical signal-based chips. The optical chip(s) and the electrical chip(s) are different layers of the stack structure, and the optical chip(s) includes optical signal paths extending at least partially laterally within the optical chip(s). Electrical signal paths are provided extending between and coupling the optical chip(s) and the electrical chips. The electrical signal paths include one or more through substrate vias (TSVs) through one or more electrical chips of the multiple electrical chips in the stack structure. In one embodiment, the optical chip(s) is configured laterally to locally distribute, via one or more paths of the electrical signal paths, a timing reference signal for one or more electrical chips in the stack. Conversion between optical and electrical signals within the stack structure occurs within the optical chip(s).

Abstract: A tunnel field-effect transistor is provided, which includes a fin-shaped, source-drain circuit structure with a source region and a drain region. The circuit structure is angled in cross-sectional elevation, and includes a first portion and a second portion. The first portion extends away from the second portion, and the source region is disposed in the first or second portion, and the drain region is disposed in the other of the first or second portion. The transistor further includes a gate electrode for gating the circuit structure and a self-aligned tunneling region. The tunneling region is self-aligned to at least a portion of the circuit structure and extends between the gate electrode and the first or second portion of the fin-shaped circuit structure, and the self-aligned tunneling region is at least partially disposed in parallel, spaced opposing relation to a control surface of the gate electrode.

Abstract: Semiconductor structures and methods of fabrication are provided. One semiconductor structure includes a substrate, a semiconductor device layer supported by the substrate, and one or more buried through substrate vias (TSVs) disposed at least partially within the substrate. The buried through substrate via(s) is buried within the semiconductor substrate, and terminates below the semiconductor device layer of the semiconductor structure, and the semiconductor device layer extends over the buried through substrate via(s), thereby providing the buried through substrate via(s) without consuming space within the semiconductor device layer. A dielectric layer may be disposed between the substrate and the semiconductor device layer, with the TSV(s) terminating at a first end within the dielectric layer. Alternatively, the semiconductor device layer may be an epitaxially-grown layer extending over the TSV(s).

Abstract: Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.

Abstract: An apparatus, system, and method for a Gigasonic Brush for cleaning surfaces is presented. One embodiment of the system includes an array of acoustic transducers coupled to a substrate where the individual acoustic transducers have sizes in the range of 9 um2 to 250,000 um2. The system may include a positioning mechanism coupled to at least one of a target surface or the array of acoustic transducers, and configured to position the array of acoustic transducers within 1 millimeter of a target surface. The system may also include a cleaning liquid supply arranged to provide cleaning liquid for coupling the array of acoustic transducers to the target surface. The system may further include a controller coupled to the array of acoustic transducers and configured to activate the array of acoustic transducers.

Abstract: Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Abstract: A band pass filter includes a first electrode, a second electrode, and a plasma generated by the first and second electrode. The plasma is confined to a region of space through which electromagnetic waves having a frequency above an intrinsic plasma frequency are transmitted, and electromagnetic waves having a frequency below the intrinsic plasma frequency are reflected. The band pass filter may be implemented in a photo lithography tool between a source module and an exposure module. The plasma of the band pass filter may be adapted to reduce IR radiation (or other out of band radiation) exposure to the exposure module by reflecting IR radiation back to the radiation source. In an extreme ultraviolet photo lithography tool, the plasma of the band pass filter may be adapted to transmit EUV radiation.

Abstract: A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via.

Abstract: Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.

Abstract: Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Abstract: Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Abstract: A process for creating a beryllium oxide film on the surface of a semiconductor material is disclosed. The process is useful for making gate dielectric layers for metal-oxide-semiconductor (MOS) devices, particularly III-V semiconductor devices.

Abstract: Apparatuses, systems, and methods for tunneling MOSFETs (TFETs) using a self-aligned heterostructure source and isolated drain. TFETs that have an abrupt junction between source and drain regions have an increased probability of carrier direct tunneling (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction.

Abstract: Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.