Abstract: Systems and methods for vertically integrating semiconductor devices are described. In one embodiment, a method comprises providing an interposer, aligning and bonding a plurality of die to a first surface of the interposer, aligning and bonding a backplate to the plurality of die, and reducing at least one portion of the interposer to create a reconstituted wafer. In another embodiment, an apparatus comprises an interposer operable to receive at least one donor semiconductor device disposed on a first surface of the interposer and aligned therewith, and at least one host semiconductor device disposed on a second surface of the interposer and aligned therewith; where the interposer allows the at least one donor and host semiconductor devices to become vertically integrated.

Abstract: An apparatus is provided for protecting a surface of interest from particle contamination, and particularly, during transitioning of the surface between atmospheric pressure and vacuum. The apparatus includes a chamber configured to receive the surface, and a protector plate configured to reside within the chamber with the surface, and inhibit particle contamination of the surface. A support mechanism is also provided suspending the protector plate away from an inner surface of the chamber. The support mechanism holds the protector plate within the chamber in spaced, opposing relation to the surface to provide a gap between the protector plate and the surface which presents a diffusion barrier to particle migration into the gap and onto the surface, thereby inhibiting particle contamination of the surface.

Abstract: The present invention provides an apparatus and a method for an ultraviolet cleaning tool. The cleaning tool includes ultraviolet source spaced apart from a surface having contaminant particles. The ultraviolet source can create ozone between the surface and the ultraviolet source which breaks the chemical bonds between particles and the surface. The apparatus includes a gas feed which introduces a gas to aid the chemical bond. Additionally, the gas feed can introduce a gas to remove the particles from the surface.

Abstract: A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact.

Abstract: Method, apparatus, and composition of matter suited for use with, for example, immersion lithography. The composition of matter includes hafnium dioxide nanoparticles having diameters less than or equal to about 15 nanometers. The apparatus includes the composition of matter, a light source, a platform for supporting a work piece, and a lens element. The method includes providing a light source, providing a lens element between the light source and a work piece, providing the composition of matter between the lens element and the work piece, and exposing the work piece to light provided by the light source by passing light from the light source through the lens element and the composition of matter to the work piece.

Abstract: Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Abstract: The present invention provides an apparatus and a method for an ultraviolet cleaning tool. The cleaning tool includes ultraviolet source spaced apart from a surface having contaminant particles. The ultraviolet source can create ozone between the surface and the ultraviolet source which breaks the chemical bonds between particles and the surface. The apparatus includes a gas feed which introduces a gas to aid the chemical bond. Additionally, the gas feed can introduce a gas to remove the particles from the surface.

Abstract: Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing a portion of the first layer deposited over the plurality of pillars, and depositing a second layer of dielectric material over the plurality of pillars, where the second layer leaves a plurality of voids between the plurality of pillars.

Abstract: A zero-order overlay target comprises a first zero-order line array fabricated on a first layer of a semiconductor structure, the first zero-order line array having a first pitch, and a second zero-order line array fabricated on a second layer of the semiconductor structure, the second zero-order line array having a second pitch. The second pitch may be different from the first pitch, and a portion of the second zero-order line array may be positioned to become optically coupled to a portion of the first zero-order line array when subject to an overlay measurement. Further, the second pitch may be variable. For example, the variable pitch may comprise a first set of features having a pitch approximately equal to the first pitch, a second set of features having a pitch different from the first pitch, and a third set of features having a pitch approximately equal to the first pitch.

Abstract: Systems and methods for in-situ reflectivity degradation monitoring of optical collectors used in extreme ultraviolet (EUV) lithography processes are described. In one embodiment, a method comprises providing a semiconductor lithography tool employing an EUV source optically coupled to a collector within a vacuum chamber, the collector providing an intermediate focus area, measuring a first signal at the EUV source, measuring a second signal at the intermediate focus area, comparing the first and second signals, and monitoring a reflectivity parameter of the collector based upon the comparison. In another embodiment, a method comprises emitting a signal from a non-EUV light source optically coupled to the collector, measuring a signal reflected by the collector, and monitoring a reflectivity parameter of the collector based upon a comparison between the emitted and measured signals.

Abstract: Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.

Abstract: Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern.

Abstract: The present invention relates generally to the fields of semiconductor lithography. More particularly, it concerns methods, compositions, and apparatuses relating to 157 nm and 193 nm soft pellicles and the use of perfluorinated polymers in the creation of pellicles.

Abstract: Systems and methods for monitoring and controlling the operation of extreme ultraviolet (EUV) sources used in semiconductor fabrication are disclosed. A method comprises providing a semiconductor fabrication apparatus having a light source that emits in-band and out-of-band radiation, taking a first out-of-band radiation measurement, taking a second out-of-band radiation measurement, and controlling the in-band radiation of the light source, at least in part, based upon a comparison of the first and second out-of-band measurements. An apparatus comprises a detector operable to detect out-of-band EUV radiation emitted by an EUV plasma source, a spectrometer coupled to the electromagnetic detector and operable to measure at least one out-of-band radiation parameter based upon the detected out-of-band EUV radiation, and a controller coupled to the spectrometer and operable to monitor and control the operation of the EUV plasma source based upon the out-of-band measurements.

Abstract: The present invention relates generally to the fields of semiconductor lithography. More particularly, it concerns methods, compositions, and apparatuses relating to 157 nm, 167 nm, 193 nm, 248 nm, 365 nm, and 436 nm soft pellicles and the use of perfluorinated polymers in the creation of pellicles.

Abstract: Apparatuses and methods for cleaning a surface comprising contaminate particles are provided. In one respect, plasma and/or a shockwave may be created in a fluid flowing through a nozzle. The nozzle, coupled to a laser source and a fluid feed may be configured to deliver the generated plasma and/or shockwave to the surface.

Abstract: Methods for determining parameters of a semiconductor material, for example, non-classical substrates such as silicon-on-insulator (SOI) substrates, strained silicon-on-insulator (sSOI) substrates, silicon-germanium-on-insulator (GeOI) substrates, and strained silicon-germanium-on-insulator (sGeOI) substrates are described. The method provides steps for transforming data corresponding to the semiconductor material from real space to reciprocal space. The critical points are isolated in the reciprocal state and corresponding critical energies of the critical points are determined. The difference between the critical energies may be used to determine a thickness of a layer of the semiconductor material, in particular, a quantum confined layer.

Abstract: Methods and systems for determining a charge trap density between a semiconductor material and a dielectric material are disclosed. In one respect, spectroscopic data of the semiconductor material may be determined and used to determine a change in dielectric function. A line shape fit of the change in the dielectric function may be applied using derivative function form. The amplitude of the line shape fit may be determined and used to determine an electric field of a space charge region of the semiconductor material. By applying Poisson's equations, the scalar potential due to the electric field in the space charge region may be determined. Subsequently, using the scalar potential the charge trap density may be determined.

Abstract: Methods for determining parameters of a semiconductor material, in particular non-classical substrates such as silicon-on-insulator (SOI) substrates, strained silicon-on-insulator (sSOI) substrates, silicon-germanium-on-insulator (GOI) substrates, and strained silicon-germanium-on-insulator (sGeOI) substrates. The method provides steps for transforming data corresponding to the semiconductor material from real space to reciprocal space. The critical points are isolated in the reciprocal state and corresponding critical energies of the critical points are determined. The difference between the critical energies may be used to determine a thickness of a layer of the semiconductor material, in particular, a quantum confined layer.

Abstract: Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.