Patents Assigned to Semiconductor Components Industries, L.L.C.
  • Patent number: 8995139
    Abstract: Provided is a circuit device in which encapsulating resin to encapsulate a circuit board is optimized in shape, and a method of manufacturing the circuit device. A hybrid integrated circuit device, which is a circuit device according to the present invention includes a circuit board, a circuit element mounted on a top surface of the circuit board, and encapsulating resin encapsulating the circuit element, and coating the top surface, side surfaces, and a bottom surface of the circuit board. In addition, the encapsulating resin is partly recessed and thereby provided with recessed areas at two sides of the circuit board. The providing of the recessed areas reduces the amount of resin to be used, and prevents the hybrid integrated circuit device from being deformed by the cure shrinkage of the encapsulating resin.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Hideyuki Sakamoto
  • Patent number: 8987054
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Darrell Truhitte
  • Patent number: 8922966
    Abstract: In one embodiment, a power supply controller is configured to use a current to detect two different operating conditions on a single input terminal.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Stephanie Conseil
  • Patent number: 8902614
    Abstract: A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, the current suppression circuit applies a voltage to the node in response to a heavy load. In another operating mode, the current suppression circuit lowers the voltage at the node in response to a light load or no load. Lowering the voltage at the node decreases the flow of bias current through the circuit element thereby lowering power loss.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Christophe Basso, Jean-Paul Louvel
  • Publication number: 20120248531
    Abstract: A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: Semiconductor Components Industries, L.L.C.
    Inventors: Takuji Miyata, Kazumasa Takenaka
  • Publication number: 20120140565
    Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.
    Type: Application
    Filed: February 2, 2012
    Publication date: June 7, 2012
    Applicant: Semiconductor Components Industries, L.L.C.
    Inventors: Sorin S. Georgescu, A. Peter Cosmin, George Smarandoiu
  • Patent number: 8139408
    Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Sorin S. Georgescu, Peter Cosmin, George Smarandoiu
  • Patent number: 8093650
    Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Sorin S. Georgescu, A. Peter Cosmin
  • Patent number: 7944299
    Abstract: A method and circuit for changing a threshold voltage of a transistor. The circuit includes a sense circuit coupled to a switching transistor, a circuit transistor and to one terminal of a resistor. The other terminal of the resistor is connected to a body contact. The switching transistor directs current along one of two different paths in response to an input voltage sensed by the sense circuit. When the switching transistor directs a first current along one path, the first current is steered towards the resistor and flows through the resistor in one direction and when the switching transistor directs a second current along the other path, the second current is directed towards the resistor and flows through the resistor in the opposite direction from the first current. Steering the currents varies the potential of a body with respect to the potential at the source of the circuit transistor.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Aravind Mangudi, Eric David Joseph, Mahbub Hasan
  • Patent number: 7920424
    Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: April 5, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Sorin S. Georgescu, A. Peter Cosmin
  • Patent number: 7915672
    Abstract: In one embodiment, a structure for a semiconductor device having a trench shield electrode includes a control pad, control runners, shield runners, and a control/shield electrode contact structure. The structure is configured to use a single level of metal to connect the various components. In another embodiment, a shield runner is placed in an offset from center configuration.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 29, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Prasad Venkatraman
  • Patent number: 7915155
    Abstract: Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: March 29, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peter Moens, Marnix Tack, Sylvie Boonen, Paul Colson
  • Patent number: 7911081
    Abstract: In embodiment, a power supply system is configured to use a linear regulator to form a regulated voltage during a standby mode and to use the regulated voltage to form another regulated voltage.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Nicolas Cyr
  • Patent number: 7902075
    Abstract: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Gordon M. Grivna, Gary H. Loechelt, John Michael Parsey, Jr., Mohammed Tanvir Quddus
  • Patent number: 7897462
    Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peter A. Burke, Duane B. Barber, Brian Pratt
  • Patent number: 7888921
    Abstract: A controller for a multi-phase switching power supply shuffles the sequence of the phases in response to a load transient to prevent synchronization of one or more phases with high-frequency load transients. The sequence may be shuffled by varying the frequency and/or sequence of the switching control signals to introduce a random variation in the phases.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: February 15, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: David A. Tobin, Xiaogang Feng, Tod F. Schiff
  • Patent number: 7876083
    Abstract: A tuner having one or more digitally controllable tuning components may be coupled to an analog feedback compensation network in a target switching power supply controller to adjust the compensation while the power supply is operating. A communication interface couples the tuner to a host having a software interface to enable a user to adjust the values of the tuning components. The tuner may include components to adjust the values of a feedback network, an input network, a ramp adjust component, etc., on the target controller.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Paul A. Perrault, Tod F. Schiff, David I. Hunter
  • Patent number: 7875964
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Patent number: 7851852
    Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Prasad Venkatraman
  • Patent number: 7852155
    Abstract: In one embodiment, a class-D amplifier (11) is configured to form first (DP) and second (DN) PWM signals each having a duty cycle that is proportional to a received analog input signal (12) and responsively to enable a switch (31, 32) to short the outputs (13, 14) of the class-D amplifier (11) together responsively to some states of the first (DP) and second (DN) PWM signals.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Hassan Chaoui