Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.

Abstract: In one embodiment, a charge pump converter is formed to use various values of an output voltage to selectively control a value of a charging current during a charging cycle of the charge pump converter.

Abstract: A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode (21) in series with a resistor (22) between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device (23) is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.

Abstract: A voltage regulator having an overload protection circuit and a method for protecting against an output voltage being less than a predetermined level. The voltage regulator has an overload protection circuit coupled between a feedback network and a regulation section. A power factor correction circuit is connected to the regulation section. An output voltage from the power factor correction circuit is fed back to the feedback network, which transmits a portion of the output voltage to the overload protection circuit. If the output voltage is less than the predetermined voltage level, a transconductance amplifier generates a current that sets an overload flag. Setting the overload flag initiates a delay timer. If the delay exceeds a predetermined amount of time, the overload protection circuit shuts down the voltage regulator.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region.

Abstract: In one embodiment, a voltage reference circuit is configured to use two differentially coupled transistors to form a delta Vbe for the voltage reference circuit.

Abstract: A method for method for inhibiting thermal run-away in a multi-phase power converter at varying load transition rates. A multi-phase power converter having an on-time is provided and the frequency of the multi-phase power converter is adjusted so that a load step period and the on time of the multi-phase power converter are in a temporal relationship. Alternatively, a load step rate is inhibited from locking onto a phase current of the multi-phase power converter by suspending an oscillator signal. In accordance with another alternative, a load step rate is inhibited from locking onto a phase current of the multi-phase power converter by suspending an oscillator signal and dithering an input signal to the oscillator.

Abstract: The invention relates to a signaling system for use in a system for monitoring and/or controlling a stack of power cells. The stack of power cells is series connected, i.e. the negative terminal of one power cell is connected to the positive electrode of the adjacent power cell. A monitoring device is associated with each power cell to monitor characteristics of the power cell (temperature, voltage). Every monitoring device is powered by the power cell it is associated. The monitoring device monitors the status of the cell (e.g. it measures the difference of potential between the positive terminal and the negative terminal of that cell but it may also measure the temperature of the power cell, the pH of the electrolyte if the power cell Ci is a battery, etc. and communicates information on the status of the cell to other monitoring devices. The monitoring devices are daisy chained.

Abstract: A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor is coupled to the digital logic cells and the capacitor. The first supply current is used to charge the capacitor while the digital logic cells are not switching. While the digital logic cells are switching, the capacitor discharges to the digital logic cells, thereby providing the digital logic cells with sufficient energy to implement high-speed switching. The capacitor minimizes voltage fluctuations within in the current limited voltage supply, such that analog circuitry can be reliably powered from a different branch of the same current mirror circuit.

Abstract: In one embodiment, a charge pump controller is configured to a charge pump controller to charge a plurality of pump capacitors during a charging time interval and to sequentially form a plurality of discharge time intervals with a different pump capacitor coupled to supply a current to a load for each discharge time interval.

Abstract: An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material disposed on the flag. Wire bonds are formed from the conductive strips on one side of the ferrite core to corresponding conductive strips on an opposing side of the ferrite core. The wire bonds and the conductive strips cooperate to form the coil of the inductor. Wire bonds electrically couple one end of the inductor to leadframe leads adjacent the semiconductor die. Wire bonds couple bond pads on the semiconductor die to the leadframe leads coupled to the inductor. An encapsulant is formed around the inductor and the semiconductor die. Alternatively, a stand-alone inductor is manufactured.

Abstract: A power supply controller (25) is configured to accurately adjust the value of an output voltage of a power supply system (10) responsively to the output voltage increasing to an undesirable value. The controller (25) accurately limits an upper value of the output voltage during a light load condition, and rapidly reduces the value of the output voltage during a light load condition, and different control signals to control the switching of the output transistors facilitates rapidly reducing the output voltage.

Abstract: The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).

Abstract: A regulator circuit receives a power supply and provides a regulated power supply output suitable for integrated circuitry. It has a controllable current source circuit, a controller and a capacitor, such that an output of the controllable current source circuit can provide a lower frequency current part of the regulated power supply output, and the capacitor can supply a higher frequency current part of the regulated power supply output. The controllable current source circuit is controlled according to feedback from the regulated power supply output, and to restrict a rate of change of the output of the controllable current source circuit. The amount of EMI noise caused by high rate of change of current in power supply lines to the regulator circuit can be reduced. This can be done more efficiently or using a smaller capacitor than known arrangements.

Abstract: In one embodiment, the bulk input voltage is used to form a reference signal that is used for controlling a switching power supply system to operate in a power overload operating mode.

Abstract: In one embodiment, a PWM controller uses the input power of a power system to regulate a duty cycle of a switching PWM signal.

Abstract: A LED driver IC includes a control module(s) for controlling one or more LED drive parameters and non-volatile memory for storing settings data for that control module(s). The control module(s) is fully integrated into the LED driver IC and does not require any control input from off-chip components or signals. Therefore, the space requirements for LED circuits that make use of the LED driver IC can be minimized. Also, the non-volatile memory storage of settings data eliminates the need for an initialization or configuration input each time the LED driver IC is powered on. The non-volatile memory can be a one-time programmable memory or can be a reprogrammable memory.

Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.

Abstract: In one embodiment, a voltage regulator uses a first current to charge a by-pass capacitor for a first time period and uses a second current after the first time period.