Abstract: A monitoring system (14, 24, 34, 50) monitors voltage of a stack of batteries (10, 20, 30.) Each battery has a plurality of cells (13). A monitoring unit (14, 24, 34) is associated with each battery and measures voltage across a selected cell. A first monitoring unit and a second monitoring unit measure the same cell, e.g. cell Cn,1 of battery 10. The first and second measurements are used to calculate a correction factor which can be used to correct a set of measurements made by one of the monitoring units (14, 24). The monitoring units (14, 24, 34) are arranged in a chain, with adjacent units in the chain being connected by a communication interface in which data is transmitted as signaling voltage levels between interface units. The interface units (16, 25) of a pair of monitoring units (14, 24) use the same signaling voltage levels.

Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Abstract: A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.

Abstract: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

Abstract: According to some embodiments, a light emitting diode (LED) power management and diagnostics history recording integrated circuit includes a power management circuit controlling a supply of power to the LED, a diagnostics detection circuit recording a diagnostics history for the LED, a non-volatile diagnostics history memory storing the diagnostics history; and an external interface for transferring externally the diagnostics history stored in the non-volatile diagnostics history memory. The diagnostics history includes diagnostics data for at least two sequential occurrences of a reoccurring fault condition. The diagnostics data may include temperature, under-voltage, over-voltage, open-circuit load, and short-circuit load indicators, among others. A diagnostics analysis system downloads the diagnostics data after a given operation period and performs maintenance decisions according to the diagnostics data.

Abstract: In one embodiment, a diagnostic circuit is used to test the on-resistance of a transistor.

Abstract: A charge pump provides a programmable multiplication factor for generating an output voltage. A first output voltage may be generated by connecting a first plurality of N capacitors in a first plurality of (N+1) configurations. A second output voltage may be generated by connecting a second plurality of M capacitors in a second plurality of M+1 configurations. The first plurality of N capacitors and the second plurality of M capacitors have one or more capacitors in common. The integers M and N may be equal, although this is not required. The first plurality of configurations is different than the second plurality of configurations, thereby providing different multiplication factors for the first and second pluralities of configurations. In one embodiment, the first plurality of (N+1) configurations results in an output voltage of about 3/4× an input voltage.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.

Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.

Abstract: A switching power supply controller includes a comparator to compare a feedback signal to a first limit and a second limit, one of which includes a ramp. Limit generators may be used to generate limit signals in response to power supply signals, control signals, and/or output signals. An error amplifier may be used to generate the feedback signal in response to an output signal and an input control signal. A switching power supply may alternatively include an oscillator that shifts the switching frequency in response to the input control signal.

Abstract: A switch drive circuit utilizes charge transfer within and/or between boost circuit and/or snubber circuits for boosted switch drives. A boost circuit may include a divider to limit a boosted signal for driving a switch. A snubber circuit may transfer charge to a boost circuit.

Abstract: In one embodiment, a filter structure that integrates one plate of a capacitor with an electrode of a transient voltage device. The filter structure includes a well region of one conductivity type formed in semiconductor substrate of an opposite conductivity type. The well region forms one plate of the capacitor and an electrode of the transient voltage suppression device. A dielectric layer is formed over a portion of the well region and a conductive layer is formed overlying the dielectric layer to provide a second plate of the capacitor. The dopant concentration of the well region provides a constant capacitance/voltage characteristic for the filter structure when a selected voltage range is applied to plates of the capacitor.

Abstract: A power controller forms drive pulses that reduces audible noise under light load conditions.

Abstract: In one embodiment, a vertical N-channel transistor is coupled in a high side configuration to control a current through an LED. A control circuit operates the vertical N-channel transistor to control a value of the current.

Abstract: In one embodiment, an error amplifier of a power supply controller is configured to receive a current sense signal prior to the current sense signal undergoing amplification.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode.

Abstract: In one embodiment, a filter structure includes first and second filter devices formed using a semiconductor substrate. A vertical ground plane structure prevents cross-coupling between the first and second filter devices.

Abstract: In one embodiment, a reference generator forms a reference signal that may have temperature and process variations. A comparator that has similar variations is used to detect a signal using the reference.

Abstract: In one embodiment, a current regulator is configured to form a first signal representative of a current flow through a power switch and to use the first signal to determine an off-time of the power switch.