Abstract: A buffer circuit (100) receives a selection signal (SFI), which selects either a first or second threshold voltage for receiving an input signal (SSI) at a logic gate (6). A switch (1) and a level-shifter (13) are used in combination to set a voltage at a node (12). The first input signal is coupled to the switch. The logic gate is coupled to the node, and the voltage level at the node sets the threshold voltage of the logic gate of the buffer circuit.

Abstract: A smart card reader (8) includes a detection circuit (26) that has a plurality of inputs (30, 38, 42) for monitoring a plurality of operating conditions of the smart card reader. A plurality of outputs (53-56) provide a plurality of sense signals (VCCOK, VCCOC, VBATOK, CRDINS). A multiplexer (60) has a plurality of sense inputs coupled to the plurality of outputs of the detection circuit. A selection input (67, 68) receives a selection signal (ADDR) for routing one of the plurality of sense signals to an output (32) as a status signal (STATUS).

Abstract: A power controller (10) of a power system switches between operating in a linear operational mode and a non-linear operational mode. The power controller (10) disables an output transistor (40) and removes a linear drive signal from the output transistor (40) to terminate operation in the linear operational mode. Prior to enabling operation in the non-linear operational mode, the power controller (10) adjusts a value of an error voltage in order to minimize overshoot in the output voltage during the mode switch.

Abstract: In an exemplary embodiment, a system (10) is formed to include a semiconductor device (11) that is formed to function as a voltage regulator. The semiconductor device (11) is formed to have a control loop that includes an amplifier (30) and a feedback transistor (19) that provide a small signal AC gain that varies inversely to a load current of an output transistor (12) in order compensate for the manner in which the output transistor (12) transconductance depends on the load current flowing through the output transistor (12).

Abstract: A semiconductor package (101) has a die (1), a leadframe (4), a bond pad (6), an encapsulation (3) and a wire bond ball (2). The wire bond ball is formed on the bond pad by bonding one end of a bond wire (7), and remainder of the bond wire is removed. Locations (23) for attaching the wire bond ball are recorded with reference to fiducials (5) on the lead frame. The encapsulation covers the die, deposits and die attach flag (24) of the lead frame. The wire bond ball is exposed where the encapsulation is removed. The locations for making openings (17) for exposing the wire bond ball is determined by recorded coordinates when the wire bond ball is formed. Exposed wire bond ball is plated, forming a lead to electrically connect to the die.

Abstract: An integrated voltage converter (104) includes a first switch (S1) that turns on with a value of a control signal (UP/DOWN) to generate a coil current (ICOIL) at a node (208) when an output voltage (VOUT) of the voltage converter is greater than a reference voltage (VBATT−&Dgr;V). A second switch (S2) coupled to the node turns on with another value of the control signal to generate the coil current when the output voltage is less than the reference voltage. The coil current discharges through the second switch to an output (202) of the voltage converter to develop the output voltage.

Abstract: A protection circuit (10) is formed to protected a load (11) when a short circuit develops during operation of the load (11). A load transistor (18) is formed to couple the load to a voltage return terminal. A disable transistor (19) is formed to disable the load transistor (18) when a short circuit occurs.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Abstract: A method of forming a power supply timing controller circuit (10, 80, 90) includes forming a bi-directional synchronization oscillator controller (11, 81, 91) to oscillate at an internal frequency. The bi-directional synchronization oscillator controller (11, 81, 91) receives an external sync signal, suspends the oscillation, begins operating at the forced frequency of the external sync signal, and begins a delay period. If another external sync signal is not received before the end of the delay period, the controller resets and once again begins oscillating at the internal frequency.

Abstract: An semiconductor device (100) comprising a first semiconductor die (120) and a leadframe (200). The leadframe includes a first laminate (210) having a bottom surface formed with a lead (220) of the semiconductor device, a second laminate (230) overlying the first laminate for mounting the semiconductor die, and an adhesive tape (250) for attaching the first and second laminates.

Abstract: A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84) adjacent to the first region is used to form an emitter region of the transistor. An interstitial trapping material (81) reduces diffusion of dopants in the base region during subsequent thermal processing.

Abstract: An integrated circuit (10) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit (13) when its temperature exceeds a predefined value. First and second current sources (18, 17) respectively produce first and second reference currents (IREF1, IREF2) representative of first and second die temperatures of the integrated circuit. A current mirror (14) has an input (19) for summing the first and second reference currents and an output (15) for providing a mirror current (IMIRROR). A detection circuit (12) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (VDET) as a function of the first and second die temperatures.

Abstract: A power factor correction device (26, 75) stores the output of an error amplifier (32) on a storage element (39). A zero crossing detector (37) detects the zero crossings of the AC input voltage and enables the power factor correction device (26, 75) to adjust the value of the voltage stored on the storage element (39).

Abstract: An amplifier (170) includes first and second depletion mode transistors (161, 162) operating in response to first and second complementary signals (VAMP+, VAMP−), respectively, which route a first current (ISTACK1) from a first supply terminal (171) to an output (169) of the amplifier. Third and fourth depletion mode transistors (163, 164) receive the first and second complementary signals to route a second current (ISTACK2) from a second supply terminal (Ground) to the output. The first and second currents are summed to produce an output signal (VAMP2).

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.

Abstract: A programmable data latch (21) is disclosed. The data latch comprises a master latch (34) operable to load data into the data latch (21) and a slave latch (36) operable to receive the data and produce the output (20) and inverted output of the data latch (21). Also provided is a plurality of programmable floating gate transistor (53, 54) wherein the “on” or “off” state of the floating gate transistor (53, 54) is determined by the data loaded into the data latch (21). A programming voltage supply (26) is supplied to the floating gate transistors (53, 54) which increases the threshold voltage of the floating gate transistor (53, 54) in the “on” state and produces a programmed transistor. The programmed transistor is operable to set the state of the data latch (21) upon subsequent use.

Abstract: An integrated circuit (100) includes a semiconductor die (102, 103) and a semiconductor package (101) that has a leadframe (20, 40, 60, 80) for mounting the semiconductor die. The leadframe includes a first laminate (20) whose bottom surface (7) is patterned with leads (106, 107, 131, 132) of the integrated circuit. A second laminate (40) has a bottom surface (3) attached to a top surface (5) of the first laminate to electrically coupling the leads to the semiconductor die.

Abstract: A power amplifier driver (16) provides control voltage inputs to power amplifier (14) at terminal (OUT). An output power control loop is implemented through directional coupler (20) and power amplifier driver (16). Power amplifier driver (16) implements a loop integration function utilizing transconductance amplifiers (60, 62) to convert a detection signal (DET) and a reference signal (REF2) to current for summing at node 58. Transconductance amplifiers (70,72) convert the error voltage generated at node (34) and bias voltage (Vmin) to current for summing at node (36) for subsequent conversion back to voltage by resistor (74). The error voltage at node (36) is buffered (26) to provide adequate current drive at terminal (OUT).