Patents Assigned to Semiconductor Components Industries, L.L.C.
  • Patent number: 6771138
    Abstract: A method of forming a power supply timing controller circuit (10, 80, 90) includes forming a bi-directional synchronization oscillator controller (11, 81, 91) to oscillate at an internal frequency. The bi-directional synchronization oscillator controller (11, 81, 91) receives an external sync signal, suspends the oscillation, begins operating at the forced frequency of the external sync signal, and begins a delay period. If another external sync signal is not received before the end of the delay period, the controller resets and once again begins oscillating at the internal frequency.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: August 3, 2004
    Assignee: Semiconductor Component Industries, L.L.C.
    Inventors: Jeffrey Dumas, Benjamin M. Rice
  • Patent number: 6768186
    Abstract: An semiconductor device (100) comprising a first semiconductor die (120) and a leadframe (200). The leadframe includes a first laminate (210) having a bottom surface formed with a lead (220) of the semiconductor device, a second laminate (230) overlying the first laminate for mounting the semiconductor die, and an adhesive tape (250) for attaching the first and second laminates.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: July 27, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: James P. Letterman, Jr., Joseph K. Fauty, Jay Allen Yoder
  • Patent number: 6764918
    Abstract: A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84) adjacent to the first region is used to form an emitter region of the transistor. An interstitial trapping material (81) reduces diffusion of dopants in the base region during subsequent thermal processing.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: July 20, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Gary H. Loechelt
  • Patent number: 6759891
    Abstract: An integrated circuit (10) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit (13) when its temperature exceeds a predefined value. First and second current sources (18, 17) respectively produce first and second reference currents (IREF1, IREF2) representative of first and second die temperatures of the integrated circuit. A current mirror (14) has an input (19) for summing the first and second reference currents and an output (15) for providing a mirror current (IMIRROR). A detection circuit (12) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (VDET) as a function of the first and second die temperatures.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: July 6, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Robert N. Dotson
  • Patent number: 6756839
    Abstract: An amplifier (170) includes first and second depletion mode transistors (161, 162) operating in response to first and second complementary signals (VAMP+, VAMP−), respectively, which route a first current (ISTACK1) from a first supply terminal (171) to an output (169) of the amplifier. Third and fourth depletion mode transistors (163, 164) receive the first and second complementary signals to route a second current (ISTACK2) from a second supply terminal (Ground) to the output. The first and second currents are summed to produce an output signal (VAMP2).
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: June 29, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Jefferson W. Hall, Jade H. Alberkrack
  • Patent number: 6756771
    Abstract: A power factor correction device (26, 75) stores the output of an error amplifier (32) on a storage element (39). A zero crossing detector (37) detects the zero crossings of the AC input voltage and enables the power factor correction device (26, 75) to adjust the value of the voltage stored on the storage element (39).
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: June 29, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Alan R. Ball, Jefferson W. Hall
  • Patent number: 6756273
    Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: June 29, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peyman Hadizad, Jina Shumate, Ali Salih
  • Patent number: 6753228
    Abstract: A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: June 22, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Misbahul Azam, Jeffrey Pearse, Daniel G. Hannoun
  • Patent number: 6747477
    Abstract: A programmable data latch (21) is disclosed. The data latch comprises a master latch (34) operable to load data into the data latch (21) and a slave latch (36) operable to receive the data and produce the output (20) and inverted output of the data latch (21). Also provided is a plurality of programmable floating gate transistor (53, 54) wherein the “on” or “off” state of the floating gate transistor (53, 54) is determined by the data loaded into the data latch (21). A programming voltage supply (26) is supplied to the floating gate transistors (53, 54) which increases the threshold voltage of the floating gate transistor (53, 54) in the “on” state and produces a programmed transistor. The programmed transistor is operable to set the state of the data latch (21) upon subsequent use.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: June 8, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Robert Maigret, Thomas Somerville
  • Patent number: 6747341
    Abstract: An integrated circuit (100) includes a semiconductor die (102, 103) and a semiconductor package (101) that has a leadframe (20, 40, 60, 80) for mounting the semiconductor die. The leadframe includes a first laminate (20) whose bottom surface (7) is patterned with leads (106, 107, 131, 132) of the integrated circuit. A second laminate (40) has a bottom surface (3) attached to a top surface (5) of the first laminate to electrically coupling the leads to the semiconductor die.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 8, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: James Knapp, Stephen St. Germain
  • Patent number: 6744313
    Abstract: A power amplifier driver (16) provides control voltage inputs to power amplifier (14) at terminal (OUT). An output power control loop is implemented through directional coupler (20) and power amplifier driver (16). Power amplifier driver (16) implements a loop integration function utilizing transconductance amplifiers (60, 62) to convert a detection signal (DET) and a reference signal (REF2) to current for summing at node 58. Transconductance amplifiers (70,72) convert the error voltage generated at node (34) and bias voltage (Vmin) to current for summing at node (36) for subsequent conversion back to voltage by resistor (74). The error voltage at node (36) is buffered (26) to provide adequate current drive at terminal (OUT).
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: June 1, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Pierre Andre Genest
  • Patent number: 6730606
    Abstract: A masking material (14) is formed on a foundation layer (12) and a substrate (10). A mask (16) is disposed onto the masking material (14) where a trench (26) is desired to be formed. An etch step removes all of the masking material (14) except at regions where the mask (16) was formed leaving a protruding portion (18) with an opening (20) on either side. An epi layer (24), is grown on the foundation layer (12) adjacent to the protruding portion (18) in the opening (20). A wet oxide etch process is used to remove the protruding portion (18) leaving a trench (26) formed in the epi layer (24). To complete the process, a silicon wet etch process is used to round off the corners at an edge (28) of the trench (26).
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: May 4, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Misbahul Azam, Jeffrey Pearse, Christopher J. Gass
  • Patent number: 6717473
    Abstract: An audio amplifier system (10) is formed to include a voltage reference (16). The voltage reference (16) is formed to utilize a filter having a first cut-off frequency when the output (14) of the voltage reference (16) is less than a first value and to use a second cut-off frequency when the output (14) is greater than the first value.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: April 6, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Patrick Bernard, Anthony Quelen, Christian Perrin
  • Patent number: 6713317
    Abstract: A method of making a semiconductor device (100) by attaching a top surface of a first laminate (630) to a bottom surface of a second laminate (650) to form a leadframe (620) and mounting a semiconductor die (102) to the leadframe to form the semiconductor device. The first semiconductor die is encapsulated with a molding compound (108) and material is removed from the first laminate to form a mold lock (120) with the molding compound.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: March 30, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: James Knapp, Stephen St. Germain
  • Patent number: 6707283
    Abstract: A switching power supply (30) includes a compensation circuit (58) which monitors a transformers (36) primary side to provide a voltage compensation signal, COMPV. A transistor inductor current, VTRAN is fed to the compensation circuit (58) to establish a DC level proportional to the peak primary side inductor current flowing through a power transistor (38). VTRAN is fed to a multiplier circuit (98). The output of the multiplier circuit (98) is scaled by a resistor (80) to establish the compensation signal, COMPV at the output to the compensation circuit (58). When at current limit, an amplifier (66) becomes saturated causing a diode (68) to reverse bias, effectively removing compensation signal COMPV from operation. An amplifier (70) falls into a linear region and a diode (74) becomes forward bias forcing compensation signal COMPC into operation providing regulation to the output of the switching power supply (30) at current limit.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: March 16, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Alan R. Ball
  • Patent number: D489338
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: May 4, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Michael Seddon, Francis Carney, Kent L. Kime