Abstract: An multi-stage error amplifier (22) of a power management system (10) is formed to insert a zero to compensate for a high frequency pole that could cause unstable outputs at some output current levels. The error amplifier (22) includes a feed-forward block (40) that isolates the capacitor (36) from other signal paths to facilitate low noise and high efficiency operation.

Abstract: A method for forming a direct chip attach (DCA) device (1) includes attaching a chip (3) to a lead frame (2). Conductive studs (22) are attached to bonding pads (13) on the chip (3) and a flag (18) on lead frame (2). The chip (3) and flag (18) are enclosed with an encapsulating layer (4), and openings (6) are formed in an upper surface (7) to expose conductive studs (22). In one embodiment, a masking layer (51) is applied to the lead frame (2), and the structure is then placed in an electroless plating apparatus (61). While in the plating apparatus (61), an injection device (66) injects plating solution (71) towards the upper surface (7) and openings (6) to enhance the formation of barrier layers (24) on the conductive studs (22). Solder bumps (9) are then attached to barrier layers (24) through the openings (6).

Abstract: A semiconductor device (20) has a first leadframe (200) with a first semiconductor die (70) electrically coupled to one of its leads. A second semiconductor die (130) is mounted to a second leadframe (300) that has a first lead (35, 150) electrically coupled to the second semiconductor die and a second lead (30, 35) mounted to the lead of the first leadframe.

Abstract: A differential amplifier (10, 60) is formed to have a propagation delay that varied responsively to a control signal received on a differential control signal input. The propagation delay is varied by changing the bias current of a pair of differential input transistor (11, 13).

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84, 85, 87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66,68) are formed along a vertical wall (84) inside of the trench (60). The source regions (66,68) have a horizontal component along the major surface (56) and a vertical component extending the vertical wall (84). The majority of the source regions (66,68) are formed along the vertical wall (84) within the trench (60). A typical aspect ratio of the vertical length of the source regions (66,68) to the horizontal width is greater than 3:1. An Inter-layer dielectric (ILD) layer (74) is formed on the gate structure (62) within the trench (60) below the major surface (56).

Abstract: A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to form a void (16).

Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).

Abstract: A method of forming a power device (10) includes forming a power transistor (27) and a pull-down transistor (28) on a semiconductor die (36). The pull-down transistor (28) is enabled to rapidly and predictably disable the power transistor (27). The pull-down transistor (28) remains enabled for a first time period during the enabling of the power transistor (27) to facilitate rapidly and predictably enabling the power transistor (27).

Abstract: A method of making a semiconductor device (10) includes depositing a first conductive layer (50) on a first surface (41) to control a channel (70) of the semiconductor device at a second surface (40) perpendicular to the first surface. The method further includes etching a first dielectric film (32) to form a gap (53) between the first surface and a control electrode (68) of the semiconductor device, and depositing a conductive material (56) in the gap to electrically connect the first conductive layer to the control electrode.

Abstract: In a dual power supply, a main power supply is shut down by providing a signal from an auxiliary power supply. To generate the shutdown signal, a load is temporarily applied to the output of the auxiliary power supply for a predetermined time. The application of the load is detected using a hysteretic comparator in the auxiliary power supply that remains in a high state for a time period that exceeds a reference time period, which is established by a timer circuit. In response to exceeding the reference time period, the shutdown signal is sent to the main power supply.

Abstract: A power controller (10) of a power system switches between operating in a linear operational mode and a non-linear operational mode. The power controller (10) disables an output transistor (40) and removes a linear drive signal from the output transistor (40) to terminate operation in the linear operational mode. Prior to enabling operation in the non-linear operational mode, the power controller (10) adjusts a value of an error voltage in order to minimize overshoot in the output voltage during the mode switch.

Abstract: A buffer circuit (100) receives a selection signal (SFI), which selects either a first or second threshold voltage for receiving an input signal (SSI) at a logic gate (6). A switch (1) and a level-shifter (13) are used in combination to set a voltage at a node (12). The first input signal is coupled to the switch. The logic gate is coupled to the node, and the voltage level at the node sets the threshold voltage of the logic gate of the buffer circuit.

Abstract: A smart card reader (8) includes a detection circuit (26) that has a plurality of inputs (30, 38, 42) for monitoring a plurality of operating conditions of the smart card reader. A plurality of outputs (53-56) provide a plurality of sense signals (VCCOK, VCCOC, VBATOK, CRDINS). A multiplexer (60) has a plurality of sense inputs coupled to the plurality of outputs of the detection circuit. A selection input (67, 68) receives a selection signal (ADDR) for routing one of the plurality of sense signals to an output (32) as a status signal (STATUS).

Abstract: In an exemplary embodiment, a system (10) is formed to include a semiconductor device (11) that is formed to function as a voltage regulator. The semiconductor device (11) is formed to have a control loop that includes an amplifier (30) and a feedback transistor (19) that provide a small signal AC gain that varies inversely to a load current of an output transistor (12) in order compensate for the manner in which the output transistor (12) transconductance depends on the load current flowing through the output transistor (12).

Abstract: A semiconductor package (101) has a die (1), a leadframe (4), a bond pad (6), an encapsulation (3) and a wire bond ball (2). The wire bond ball is formed on the bond pad by bonding one end of a bond wire (7), and remainder of the bond wire is removed. Locations (23) for attaching the wire bond ball are recorded with reference to fiducials (5) on the lead frame. The encapsulation covers the die, deposits and die attach flag (24) of the lead frame. The wire bond ball is exposed where the encapsulation is removed. The locations for making openings (17) for exposing the wire bond ball is determined by recorded coordinates when the wire bond ball is formed. Exposed wire bond ball is plated, forming a lead to electrically connect to the die.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: An integrated voltage converter (104) includes a first switch (S1) that turns on with a value of a control signal (UP/DOWN) to generate a coil current (ICOIL) at a node (208) when an output voltage (VOUT) of the voltage converter is greater than a reference voltage (VBATT−&Dgr;V). A second switch (S2) coupled to the node turns on with another value of the control signal to generate the coil current when the output voltage is less than the reference voltage. The coil current discharges through the second switch to an output (202) of the voltage converter to develop the output voltage.

Abstract: A protection circuit (10) is formed to protected a load (11) when a short circuit develops during operation of the load (11). A load transistor (18) is formed to couple the load to a voltage return terminal. A disable transistor (19) is formed to disable the load transistor (18) when a short circuit occurs.

Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.