Patents Assigned to Semiconductor Components Industries, L.L.C.
  • Patent number: 7208385
    Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: April 24, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Zia Hossain, Mohamed Imam, Joe Fulton
  • Patent number: 7205605
    Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: April 17, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peyman Hadizad, Jina Shumate, Ali Salih
  • Patent number: 7205583
    Abstract: A thyristor and a method for manufacturing the thyristor that includes providing a semiconductor substrate that has first and second major surfaces. A first doped region is formed in the semiconductor substrate, wherein the first doped extends from the first major surface into the semiconductor substrate. The first doped region has a vertical boundary that has a notched portion. A second doped region is formed in first doped region, wherein the second doped region extends from the first major surface into the first doped region. A third doped region is formed in the semiconductor substrate, wherein the third doped region extends from the second major surface into the semiconductor substrate.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: April 17, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Emmanuel Saucedo-Flores
  • Patent number: 7202106
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Patent number: 7202105
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Patent number: 7196549
    Abstract: In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: March 27, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Ira E. Baskett
  • Patent number: 7192814
    Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: March 20, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Prasad Venkatraman
  • Patent number: 7189608
    Abstract: In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 13, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Prasad Venkatraman, Irene S. Wan
  • Patent number: 7189610
    Abstract: In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: March 13, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: John David Moran, Blanca Estela Kruse, Jose Rogelio Moreno
  • Patent number: 7180170
    Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: February 20, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Phillip C. Celaya, James S. Donley, Stephen C. St. Germain
  • Patent number: 7157959
    Abstract: In one embodiment, a self-gated transistor includes a sensing portion that generates a sense signal that is used to drive the self-gated transistor.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 2, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Alan R. Ball, Paul J. Harriman, Stephen Meek, Suzanne Nee
  • Patent number: 7138315
    Abstract: A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: November 21, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Narayan Raja, Roger P. Stout
  • Patent number: 7135356
    Abstract: A seconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to expose a portion of the second surface to reveal information pertaining to the semiconductor device. The coating layer is patterned by directing a radiation beam (30) such as a laser to selectively remove material from the coating layer.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: November 14, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Michael Seddon, Francis Carney
  • Patent number: 7135924
    Abstract: In one embodiment, a pair of differential amplifiers have outputs coupled together. A signal received on one input results in signals coupled to the outputs that substantially cancel each other at the outputs.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: November 14, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Ira E. Baskett
  • Patent number: 7132857
    Abstract: A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is coupled for shifting the common mode potential of the input signal to produce a shifted signal (VSH0, VSH1). A second gate (22) has an input (27, 28) that receives the shifted signal and an output coupled to the output of the first gate.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: November 7, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Kevin Joseph Jurek
  • Patent number: 7129544
    Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: October 31, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Peyman Hadizad
  • Patent number: 7129781
    Abstract: In one embodiment, an ECL logic device uses a capacitor to couple a positive voltage to an output and reduce the rise time of the output signal.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: October 31, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Ira E. Baskett
  • Patent number: 7126166
    Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: October 24, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Rajesh S. Nair, Shanghui Larry Tu, Zia Hossain, Mohammed Tanvir Quddus
  • Patent number: 7126388
    Abstract: In one embodiment, a power MOSFET driver uses two different voltages for the operating voltage of the two output drivers of the power MOSFET driver.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: October 24, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Paul J. Harriman
  • Patent number: 7123494
    Abstract: A power factor correction (PFC) circuit (10) includes a pulse width modulator (31) operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node (32). The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output (30). An oscillator (35) generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input (39) for sensing the input signal to modify the clock period.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: October 17, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Joel Turchi